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White Rabbit Trigger Distribution
Commits
90d51cfa
Commit
90d51cfa
authored
Jan 30, 2019
by
Dimitris Lampridis
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hdl: introduce spec150t_adc reference design
parent
42c26287
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.gitignore
hdl/syn/wrtd_ref_spec150t_adc/.gitignore
+5
-0
Manifest.py
hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
+36
-0
syn_extra_steps.tcl
hdl/syn/wrtd_ref_spec150t_adc/syn_extra_steps.tcl
+26
-0
wrtd_ref_spec150t_adc.ucf
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
+522
-0
Manifest.py
hdl/top/wrtd_ref_spec150t_adc/Manifest.py
+20
-0
carrier_csr.vhd
hdl/top/wrtd_ref_spec150t_adc/carrier_csr.vhd
+241
-0
carrier_csr_wbgen2_pkg.vhd
hdl/top/wrtd_ref_spec150t_adc/carrier_csr_wbgen2_pkg.vhd
+95
-0
dma_eic.vhd
hdl/top/wrtd_ref_spec150t_adc/dma_eic.vhd
+320
-0
.gitignore
hdl/top/wrtd_ref_spec150t_adc/wb_gen/.gitignore
+4
-0
Makefile
hdl/top/wrtd_ref_spec150t_adc/wb_gen/Makefile
+11
-0
carrier_csr.wb
hdl/top/wrtd_ref_spec150t_adc/wb_gen/carrier_csr.wb
+134
-0
dma_eic.wb
hdl/top/wrtd_ref_spec150t_adc/wb_gen/dma_eic.wb
+21
-0
wrtd_ref_spec150t_adc.vhd
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
+1150
-0
No files found.
hdl/syn/wrtd_ref_spec150t_adc/.gitignore
0 → 100644
View file @
90d51cfa
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
0 → 100644
View file @
90d51cfa
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board
=
"spec"
target
=
"xilinx"
action
=
"synthesis"
syn_device
=
"xc6slx150t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"wrtd_ref_spec150t_adc"
syn_project
=
"wrtd_ref_spec150t_adc.xise"
syn_tool
=
"ise"
fetchto
=
"../../../dependencies"
ctrls
=
[
"bank3_64b_32b"
]
syn_post_project_cmd
=
(
"$(TCL_INTERPRETER) "
+
\
fetchto
+
"/general-cores/tools/sdb_desc_gen.tcl "
+
\
syn_tool
+
" $(PROJECT_FILE);"
\
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
files
=
[
"wrtd_ref_spec150t_adc.ucf"
,
]
modules
=
{
"local"
:
[
"../../top/wrtd_ref_spec150t_adc"
,
],
}
hdl/syn/wrtd_ref_spec150t_adc/syn_extra_steps.tcl
0 → 100644
View file @
90d51cfa
# get project file from 1st command-line argument
set
project_file
[
lindex
$argv
0
]
if
{
!
[
file
exists
$project
_file
]}
{
report ERROR
"Missing file
$project
_file, exiting."
exit -1
}
xilinx::project open
$project
_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set
"Enable Multi-Threading"
"2"
-process
"Map"
xilinx::project set
"Enable Multi-Threading"
"4"
-process
"Place & Route"
xilinx::project set
"Pack I/O Registers into IOBs"
"Yes"
xilinx::project set
"Pack I/O Registers/Latches into IOBs"
"For Inputs and Outputs"
xilinx::project set
"Register Balancing"
"Yes"
xilinx::project set
"Register Duplication Map"
"On"
xilinx::project save
xilinx::project close
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
0 → 100644
View file @
90d51cfa
This diff is collapsed.
Click to expand it.
hdl/top/wrtd_ref_spec150t_adc/Manifest.py
0 → 100644
View file @
90d51cfa
files
=
[
"wrtd_ref_spec150t_adc.vhd"
,
"carrier_csr_wbgen2_pkg.vhd"
,
"carrier_csr.vhd"
,
"dma_eic.vhd"
,
]
fetchto
=
"../../../dependencies"
modules
=
{
"git"
:
[
"git://ohwr.org/hdl-core-lib/general-cores.git"
,
"git://ohwr.org/hdl-core-lib/wr-cores.git"
,
"git://ohwr.org/hdl-core-lib/urv-core.git"
,
"git://ohwr.org/hdl-core-lib/mock-turtle.git"
,
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git"
,
"git://ohwr.org/hdl-core-lib/gn4124-core.git"
,
"git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git"
,
],
}
hdl/top/wrtd_ref_spec150t_adc/carrier_csr.vhd
0 → 100644
View file @
90d51cfa
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Jan 30 13:16:24 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
carrier_csr_wbgen2_pkg
.
all
;
entity
carrier_csr
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
regs_i
:
in
t_carrier_csr_in_registers
;
regs_o
:
out
t_carrier_csr_out_registers
);
end
carrier_csr
;
architecture
syn
of
carrier_csr
is
signal
carrier_csr_ctrl_led_green_int
:
std_logic
;
signal
carrier_csr_ctrl_led_red_int
:
std_logic
;
signal
carrier_csr_ctrl_dac_clr_n_int
:
std_logic
;
signal
carrier_csr_rst_fmc0_int
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
1
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
carrier_csr_ctrl_led_green_int
<=
'0'
;
carrier_csr_ctrl_led_red_int
<=
'0'
;
carrier_csr_ctrl_dac_clr_n_int
<=
'0'
;
carrier_csr_rst_fmc0_int
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
ack_in_progress
<=
'0'
;
else
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
1
downto
0
)
is
when
"00"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
3
downto
0
)
<=
regs_i
.
carrier_pcb_rev_i
;
rddata_reg
(
15
downto
4
)
<=
regs_i
.
carrier_reserved_i
;
rddata_reg
(
31
downto
16
)
<=
regs_i
.
carrier_type_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
regs_i
.
stat_fmc_pres_i
;
rddata_reg
(
1
)
<=
regs_i
.
stat_p2l_pll_lck_i
;
rddata_reg
(
2
)
<=
regs_i
.
stat_sys_pll_lck_i
;
rddata_reg
(
3
)
<=
regs_i
.
stat_ddr3_cal_done_i
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10"
=>
if
(
wb_we_i
=
'1'
)
then
carrier_csr_ctrl_led_green_int
<=
wrdata_reg
(
0
);
carrier_csr_ctrl_led_red_int
<=
wrdata_reg
(
1
);
carrier_csr_ctrl_dac_clr_n_int
<=
wrdata_reg
(
2
);
end
if
;
rddata_reg
(
0
)
<=
carrier_csr_ctrl_led_green_int
;
rddata_reg
(
1
)
<=
carrier_csr_ctrl_led_red_int
;
rddata_reg
(
2
)
<=
carrier_csr_ctrl_dac_clr_n_int
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11"
=>
if
(
wb_we_i
=
'1'
)
then
carrier_csr_rst_fmc0_int
<=
wrdata_reg
(
0
);
end
if
;
rddata_reg
(
0
)
<=
carrier_csr_rst_fmc0_int
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
case
;
end
if
;
end
if
;
end
if
;
end
process
;
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
-- PCB revision
-- Reserved register
-- Carrier type
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
-- DDR3 calibration status
-- Green LED
regs_o
.
ctrl_led_green_o
<=
carrier_csr_ctrl_led_green_int
;
-- Red LED
regs_o
.
ctrl_led_red_o
<=
carrier_csr_ctrl_led_red_int
;
-- DAC clear
regs_o
.
ctrl_dac_clr_n_o
<=
carrier_csr_ctrl_dac_clr_n_int
;
-- State of the reset line
regs_o
.
rst_fmc0_o
<=
carrier_csr_rst_fmc0_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
wb_err_o
<=
'0'
;
wb_rty_o
<=
'0'
;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
hdl/top/wrtd_ref_spec150t_adc/carrier_csr_wbgen2_pkg.vhd
0 → 100644
View file @
90d51cfa
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../carrier_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Jan 30 13:16:24 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
package
carrier_csr_wbgen2_pkg
is
-- Input registers (user design -> WB slave)
type
t_carrier_csr_in_registers
is
record
carrier_pcb_rev_i
:
std_logic_vector
(
3
downto
0
);
carrier_reserved_i
:
std_logic_vector
(
11
downto
0
);
carrier_type_i
:
std_logic_vector
(
15
downto
0
);
stat_fmc_pres_i
:
std_logic
;
stat_p2l_pll_lck_i
:
std_logic
;
stat_sys_pll_lck_i
:
std_logic
;
stat_ddr3_cal_done_i
:
std_logic
;
end
record
;
constant
c_carrier_csr_in_registers_init_value
:
t_carrier_csr_in_registers
:
=
(
carrier_pcb_rev_i
=>
(
others
=>
'0'
),
carrier_reserved_i
=>
(
others
=>
'0'
),
carrier_type_i
=>
(
others
=>
'0'
),
stat_fmc_pres_i
=>
'0'
,
stat_p2l_pll_lck_i
=>
'0'
,
stat_sys_pll_lck_i
=>
'0'
,
stat_ddr3_cal_done_i
=>
'0'
);
-- Output registers (WB slave -> user design)
type
t_carrier_csr_out_registers
is
record
ctrl_led_green_o
:
std_logic
;
ctrl_led_red_o
:
std_logic
;
ctrl_dac_clr_n_o
:
std_logic
;
rst_fmc0_o
:
std_logic
;
end
record
;
constant
c_carrier_csr_out_registers_init_value
:
t_carrier_csr_out_registers
:
=
(
ctrl_led_green_o
=>
'0'
,
ctrl_led_red_o
=>
'0'
,
ctrl_dac_clr_n_o
=>
'0'
,
rst_fmc0_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_carrier_csr_in_registers
)
return
t_carrier_csr_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
end
package
;
package
body
carrier_csr_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'1'
)
then
tmp
(
i
):
=
'1'
;
else
tmp
(
i
):
=
'0'
;
end
if
;
end
loop
;
return
tmp
;
end
function
;
function
"or"
(
left
,
right
:
t_carrier_csr_in_registers
)
return
t_carrier_csr_in_registers
is
variable
tmp
:
t_carrier_csr_in_registers
;
begin
tmp
.
carrier_pcb_rev_i
:
=
f_x_to_zero
(
left
.
carrier_pcb_rev_i
)
or
f_x_to_zero
(
right
.
carrier_pcb_rev_i
);
tmp
.
carrier_reserved_i
:
=
f_x_to_zero
(
left
.
carrier_reserved_i
)
or
f_x_to_zero
(
right
.
carrier_reserved_i
);
tmp
.
carrier_type_i
:
=
f_x_to_zero
(
left
.
carrier_type_i
)
or
f_x_to_zero
(
right
.
carrier_type_i
);
tmp
.
stat_fmc_pres_i
:
=
f_x_to_zero
(
left
.
stat_fmc_pres_i
)
or
f_x_to_zero
(
right
.
stat_fmc_pres_i
);
tmp
.
stat_p2l_pll_lck_i
:
=
f_x_to_zero
(
left
.
stat_p2l_pll_lck_i
)
or
f_x_to_zero
(
right
.
stat_p2l_pll_lck_i
);
tmp
.
stat_sys_pll_lck_i
:
=
f_x_to_zero
(
left
.
stat_sys_pll_lck_i
)
or
f_x_to_zero
(
right
.
stat_sys_pll_lck_i
);
tmp
.
stat_ddr3_cal_done_i
:
=
f_x_to_zero
(
left
.
stat_ddr3_cal_done_i
)
or
f_x_to_zero
(
right
.
stat_ddr3_cal_done_i
);
return
tmp
;
end
function
;
end
package
body
;
hdl/top/wrtd_ref_spec150t_adc/dma_eic.vhd
0 → 100644
View file @
90d51cfa
This diff is collapsed.
Click to expand it.
hdl/top/wrtd_ref_spec150t_adc/wb_gen/.gitignore
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90d51cfa
*
!.gitignore
!*.wb
!Makefile
hdl/top/wrtd_ref_spec150t_adc/wb_gen/Makefile
0 → 100644
View file @
90d51cfa
WBGEN2
=
$(
shell
which wbgen2
)
RTL
=
..
all
:
carrier_csr dma_eic
carrier_csr
:
$(WBGEN2)
-l
vhdl
-H
record
-V
$(RTL)
/
$@
.vhd
-p
$(RTL)
/
$@
_wbgen2_pkg.vhd
$@
.wb
dma_eic
:
$(WBGEN2)
-l
vhdl
-V
$(RTL)
/
$@
.vhd
$@
.wb
hdl/top/wrtd_ref_spec150t_adc/wb_gen/carrier_csr.wb
0 → 100644
View file @
90d51cfa
peripheral {
name = "Carrier control and status registers";
description = "Wishbone slave for control and status registers related to the FMC carrier";
hdl_entity = "carrier_csr";
prefix = "carrier_csr";
reg {
name = "Carrier type and PCB version";
prefix = "carrier";
field {
name = "PCB revision";
description = "Binary coded PCB layout revision.";
prefix = "pcb_rev";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved register";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 12;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Carrier type";
description = "Carrier type identifier\n1 = SPEC\n2 = SVEC\n3 = VFC\n4 = SPEXI";
prefix = "type";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
field {
name = "FMC presence";
description = "0: FMC slot is populated\n1: FMC slot is not populated.";
prefix = "fmc_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "GN4142 core P2L PLL status";
description = "0: not locked\n1: locked.";
prefix = "p2l_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "System clock PLL status";
description = "0: not locked\n1: locked.";
prefix = "sys_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DDR3 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr3_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control";
prefix = "ctrl";
field {
name = "Green LED";
description = "Manual control of the front panel green LED (unused in the fmc-adc application)";
prefix = "led_green";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Red LED";
description = "Manual control of the front panel red LED (unused in the fmc-adc application)";
prefix = "led_red";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DAC clear";
description = "Active low clear signal for VCXO DACs";
prefix = "dac_clr_n";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reset Register";
prefix = "rst";
description = "Controls software reset of the mezzanine including the ddr interface and the time-tagging core.";
field {
name = "State of the reset line";
description = "write 0: Normal FMC operation\
write 1: FMC is held in reset";
type = BIT;
size = 1;
prefix = "fmc0";
access_bus = WRITE;
access_dev = READ;
};
};
};
hdl/top/wrtd_ref_spec150t_adc/wb_gen/dma_eic.wb
0 → 100644
View file @
90d51cfa
peripheral {
name = "GN4124 DMA enhanced interrupt controller";
description = "Enhanced interrrupt controller for GN4124 DMA.";
hdl_entity = "dma_eic";
prefix = "dma_eic";
irq {
name = "DMA done interrupt";
description = "DMA done interrupt line (rising edge sensitive).";
prefix = "dma_done";
trigger = EDGE_RISING;
};
irq {
name = "DMA error interrupt";
description = "DMA error interrupt line (rising edge sensitive).";
prefix = "dma_error";
trigger = EDGE_RISING;
};
};
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
0 → 100644
View file @
90d51cfa
This diff is collapsed.
Click to expand it.
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