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White Rabbit Trigger Distribution
Commits
91db04c0
Commit
91db04c0
authored
Dec 20, 2018
by
Tristan Gingold
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Adjust builder for svec_adc.
parent
a6d319ce
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4 changed files
with
15 additions
and
18 deletions
+15
-18
top.vhd
builder/fmc-adc-100m14b4cha/top.vhd
+4
-4
svec_adc_top.vhd
builder/hdl/top/svec_adc/svec_adc_top.vhd
+7
-8
top.vhd
builder/svec/top.vhd
+0
-3
wrtd_builder.py
builder/wrtd_builder.py
+4
-3
No files found.
builder/fmc-adc-100m14b4cha/top.vhd
View file @
91db04c0
...
...
@@ -98,7 +98,7 @@ use work.ddr3_ctrl_pkg.all;
name
=>
"WB-DDR-Addr-Access "
)));
[
sdb
-
layout
]
c_WB_SLAVE_FMC
{
n
}_
ADC
=>
f_sdb_embed_bridge
(
c_FMC
{
n
}_
BRIDGE_SDB
,
x"{addr}
"
),
c_WB_SLAVE_FMC
{
n
}_
ADC
=>
f_sdb_embed_bridge
(
c_FMC
{
n
}_
BRIDGE_SDB
,
x"{addr}"
or
x"2000
"
),
c_WB_SLAVE_FMC
{
n
}_
DDR_ADR
=>
f_sdb_embed_device
(
c_WB_DDR
{
n
}_
ADR_SDB
,
x"{addr}"
or
x"4000"
),
c_WB_SLAVE_FMC
{
n
}_
DDR_DAT
=>
f_sdb_embed_device
(
c_WB_DDR
{
n
}_
DAT_SDB
,
x"{addr}"
or
x"5000"
),
[
decls
]
...
...
@@ -276,7 +276,7 @@ use work.ddr3_ctrl_pkg.all;
cmp_ddr
{
n
}_
ctrl_bank
:
ddr3_ctrl
generic
map
(
g_RST_ACT_LOW
=>
0
,
-- active high reset (simpler internal logic)
g_RST_ACT_LOW
=>
1
,
-- active high reset (simpler internal logic)
g_BANK_PORT_SELECT
=>
f_ddr
{
n
}_
bank_sel
,
g_MEMCLK_PERIOD
=>
3000
,
g_SIMULATION
=>
c_FMC
{
n
}_
SIMULATION_STR
,
...
...
builder/hdl/top/svec_adc/svec_adc_top.vhd
View file @
91db04c0
...
...
@@ -44,6 +44,7 @@ use work.wr_board_pkg.all;
use
work
.
fmc_adc_mezzanine_pkg
.
all
;
use
work
.
ddr3_ctrl_pkg
.
all
;
entity
svec_adc_top
is
generic
(
g_WR_DPRAM_INITF
:
string
:
=
"../../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram"
;
...
...
@@ -333,12 +334,9 @@ architecture arch of svec_adc_top is
-- Primary wishbone crossbar layout
constant
c_WB_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_SLAVES
+
1
downto
0
)
:
=
(
c_WB_SLAVE_VIC
=>
f_sdb_embed_device
(
c_XWB_VIC_SDB
,
x"00002000"
),
c_WB_SLAVE_FMC0_ADC
=>
f_sdb_embed_bridge
(
c_FMC0_BRIDGE_SDB
,
x"00010000"
or
x"2000"
),
c_WB_SLAVE_FMC0_DDR_ADR
=>
f_sdb_embed_device
(
c_WB_DDR0_ADR_SDB
,
x"00010000"
or
x"4000"
),
c_WB_SLAVE_FMC0_DDR_DAT
=>
f_sdb_embed_device
(
c_WB_DDR0_DAT_SDB
,
x"00010000"
or
x"5000"
),
c_WB_SLAVE_FMC0_ADC
=>
f_sdb_embed_bridge
(
c_FMC0_BRIDGE_SDB
,
x"00010000"
or
x"2000"
),
c_WB_SLAVE_FMC0_DDR_ADR
=>
f_sdb_embed_device
(
c_WB_DDR0_ADR_SDB
,
x"00010000"
or
x"4000"
),
c_WB_SLAVE_FMC0_DDR_DAT
=>
f_sdb_embed_device
(
c_WB_DDR0_DAT_SDB
,
x"00010000"
or
x"5000"
),
c_WB_SLAVE_MT
=>
f_sdb_embed_device
(
c_MOCK_TURTLE_SDB
,
x"00020000"
),
c_WB_SLAVE_WRC
=>
f_sdb_embed_bridge
(
c_wrc_bridge_sdb
,
x"00040000"
),
...
...
@@ -1148,6 +1146,7 @@ begin -- architecture arch
cnx_slave_out
(
c_WB_SLAVE_FMC0_DDR_ADR
)
.
rty
<=
'0'
;
cnx_slave_out
(
c_WB_SLAVE_FMC0_DDR_ADR
)
.
stall
<=
'0'
;
-- Note: g_address/g_mask index direction is to, master_i/master_o is downto
cpu0_crossbar
:
xwb_crossbar
generic
map
(
g_num_masters
=>
1
,
...
...
@@ -1164,7 +1163,7 @@ begin -- architecture arch
slave_o
(
0
)
=>
fmc_dp_wb_in
(
0
),
master_i
(
1
)
=>
wb_adc0_trigout_slave_out
,
master_i
(
0
)
=>
wb_adc0_trigin_slave_out
,
master_o
(
1
)
=>
wb_adc0_trigout_slave_in
);
master_o
(
1
)
=>
wb_adc0_trigout_slave_in
,
master_o
(
0
)
=>
wb_adc0_trigin_slave_in
);
...
...
builder/svec/top.vhd
View file @
91db04c0
...
...
@@ -43,9 +43,6 @@ use work.wr_xilinx_pkg.all;
use
work
.
wr_board_pkg
.
all
;
{
use
}
library
unisim
;
use
unisim
.
vcomponents
.
all
;
entity
{
name
}_
top
is
generic
(
g_WR_DPRAM_INITF
:
string
:
=
"{topdir}/wr-cores/bin/wrpc/wrc_phy8.bram"
;
...
...
builder/wrtd_builder.py
View file @
91db04c0
...
...
@@ -151,6 +151,7 @@ def generate_cpu_xbar_hdl(f, templates):
templates
[
'body'
]
+=
txt
else
:
txt
=
"""
-- Note: g_address/g_mask index direction is to, master_i/master_o is downto
cpu{}_crossbar : xwb_crossbar
generic map (
g_num_masters => 1,
...
...
@@ -166,9 +167,9 @@ def generate_cpu_xbar_hdl(f, templates):
rst_n_i => rst_sys_62m5_n,
slave_i(0) => fmc_dp_wb_out({}),
slave_o(0) => fmc_dp_wb_in({})"""
.
format
(
k
,
k
)
for
s
in
r
ange
(
len
(
slaves
)):
for
s
in
r
eversed
(
range
(
len
(
slaves
)
)):
txt
+=
',
\n
master_i({}) => {}_out'
.
format
(
s
,
slaves
[
s
])
for
s
in
r
ange
(
len
(
slaves
)):
for
s
in
r
eversed
(
range
(
len
(
slaves
)
)):
txt
+=
',
\n
master_o({}) => {}_in'
.
format
(
s
,
slaves
[
s
])
txt
+=
");
\n
"
templates
[
'body'
]
+=
txt
...
...
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