Commit a8188baf authored by Dimitris Lampridis's avatar Dimitris Lampridis

sim: rename wrtd-system testbench to list

parent 2b48ab77
......@@ -3,7 +3,7 @@
#
# Author: Adam Wujek, CERN 2017
TB_DIRS=wrtd-system
TB_DIRS=list
test_results_xml=test_results.xml
.PHONY: $(TB_DIRS)
......
//
// unit name: WrtdDriver
// unit name: ListDriver
//
// description: A SystemVerilog Class to provide an abstraction of a complete
// WRTD system.
// LIST system.
//
//------------------------------------------------------------------------------
// Copyright CERN 2018
......@@ -18,18 +18,18 @@
// and limitations under the License.
//------------------------------------------------------------------------------
`ifndef __WRTD_DRIVER_INCLUDED
`define __WRTD_DRIVER_INCLUDED
`ifndef __LIST_DRIVER_INCLUDED
`define __LIST_DRIVER_INCLUDED
`include "mock_turtle_driver.svh"
`define WRTD_HMQ_LOG_SLOT 0
`define LIST_HMQ_LOG_SLOT 0
typedef struct {
uint32_t system;
uint32_t source_port;
uint32_t trigger;
} wrtd_trig_id;
} list_trig_id;
typedef struct {
uint64_t seconds;
......@@ -43,7 +43,7 @@ typedef enum {
OVERFLOW = 1,
NO_WR = 2,
TIMEOUT = 3
} wrtd_log_miss_reason;
} list_log_miss_reason;
typedef enum {
RAW = (1 << 0),
......@@ -52,25 +52,25 @@ typedef enum {
FILTERED = (1 << 3),
EXECUTED = (1 << 4),
MISSED = (1 << 5)
} wrtd_log_type;
} list_log_type;
typedef enum {
WRTD_IN = 2,
WRTD_OUT = 6
} wrtd_log_origin;
LIST_IN = 2,
LIST_OUT = 6
} list_log_origin;
class WrtdLogMsg;
wrtd_log_origin origin;
wrtd_log_type ltype;
class ListLogMsg;
list_log_origin origin;
list_log_type ltype;
uint32_t seq;
int channel;
wrtd_trig_id id;
list_trig_id id;
wr_timestamp ts;
wrtd_log_miss_reason miss_reason;
list_log_miss_reason miss_reason;
function new ( MQueueMsg msg );
this.origin = wrtd_log_origin'(msg.header.msg_id);
this.ltype = wrtd_log_type'(msg.data[0]);
this.origin = list_log_origin'(msg.header.msg_id);
this.ltype = list_log_type'(msg.data[0]);
this.seq = msg.data[1];
this.channel = msg.data[2];
this.id.system = msg.data[3];
......@@ -80,7 +80,7 @@ class WrtdLogMsg;
this.ts.ticks = msg.data[8];
this.ts.frac = msg.data[9];
if ( this.ltype == MISSED )
this.miss_reason = wrtd_log_miss_reason'(msg.data[10]);
this.miss_reason = list_log_miss_reason'(msg.data[10]);
else
this.miss_reason = NOT_MISSED;
endfunction // new
......@@ -104,9 +104,9 @@ class WrtdLogMsg;
return str;
endfunction // tostring
endclass // WrtdLogMsg
endclass // ListLogMsg
class WrtdDriver;
class ListDriver;
protected string name;
protected int hmq_log_slot;
protected MockTurtleDriver mt;
......@@ -145,10 +145,10 @@ class WrtdDriver;
endtask // init
task check_log_queue ( int core );
WrtdLogMsg log_msg;
ListLogMsg log_msg;
MQueueMsg msg;
msg = new ( core, `WRTD_HMQ_LOG_SLOT );
while ( mt.hmq_pending_messages ( core, `WRTD_HMQ_LOG_SLOT ) )
msg = new ( core, `LIST_HMQ_LOG_SLOT );
while ( mt.hmq_pending_messages ( core, `LIST_HMQ_LOG_SLOT ) )
begin
mt.hmq_receive_message ( msg );
log_msg = new ( msg );
......@@ -164,6 +164,6 @@ class WrtdDriver;
join
endtask // update
endclass // WrtdDriver
endclass // ListDriver
`endif // `ifndef __WRTD_DRIVER_INCLUDED
`endif // `ifndef __LIST_DRIVER_INCLUDED
......@@ -23,7 +23,7 @@
// and limitations under the License.
//------------------------------------------------------------------------------
`include "wrtd_driver.svh"
`include "list_driver.svh"
`include "vhd_wishbone_master.svh"
`timescale 1ns/10fs
......@@ -242,7 +242,7 @@ module main;
const uint64_t mt_base = 'h2_0000;
//
// WRTD transmitter (TDC)
// LIST transmitter (TDC)
//
simple_tdc_driver
......@@ -304,7 +304,7 @@ module main;
IMockTurtleIRQ IrqMonitorA (`MT_ATTACH_IRQ(DUT_A.cmp_mock_turtle));
WrtdDriver drvA;
ListDriver drvA;
initial begin
......@@ -323,7 +323,7 @@ module main;
end // initial begin DUTA
//
// WRTD receiver (Fine Delay)
// LIST receiver (Fine Delay)
//
simple_fdelay_mon
......@@ -370,7 +370,7 @@ module main;
IMockTurtleIRQ IrqMonitorB (`MT_ATTACH_IRQ(DUT_B.cmp_mock_turtle));
WrtdDriver drvB;
ListDriver drvB;
initial begin
......
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