hdl: add gitignore to spec_adc synthesis folder and update header in top level hdl file

aad4d61a · Dimitris Lampridis · fc12608f · aad4d61a · aad4d61a
Commit aad4d61a authored Jan 17, 2019 by Dimitris Lampridis
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Showing with 14 additions and 11 deletions

.gitignore builder/hdl/syn/spec_adc/.gitignore +5 -0

spec_adc_top.vhd builder/hdl/top/spec_adc/spec_adc_top.vhd +9 -11

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--- a/builder/hdl/syn/spec_adc/.gitignore
+++ b/builder/hdl/syn/spec_adc/.gitignore
+*
+!.gitignore
+!Manifest.py
+!*.ucf
+!syn_extra_steps.tcl
--- a/builder/hdl/top/spec_adc/spec_adc_top.vhd
+++ b/builder/hdl/top/spec_adc/spec_adc_top.vhd
 --------------------------------------------------------------------------------
 -- CERN BE-CO-HT
-- LHC Instability Trigger Distribution (LIST)
-- https://ohwr.org/projects/list
+-- White Rabbit Trigger Distribution (WRTD)
+-- https://ohwr.org/projects/wrtd
 --------------------------------------------------------------------------------
 --
-- unit name:   spec_list_top
+-- unit name:   spec_adc_top
 --
-- description: Top entity for LHC Instability Trigger Distribution project
+-- description: Top entity for the SPEC ADC
 --
-- Top level design of the SVEC-based LIST WR trigger distribution node, with
-- an FMC TDC in slot and an FMC Fine Delay in slot 2.
+-- Top level design of the SPEC-based FMC-ADC WR trigger distribution node
 --
 --------------------------------------------------------------------------------
-- Copyright CERN 2014-2018
+-- Copyright CERN 2018-2019
 --------------------------------------------------------------------------------
 -- Copyright and related rights are licensed under the Solderpad Hardware
 -- License, Version 2.0 (the "License"); you may not use this file except
@@ -47,13 +46,13 @@ use work.ddr3_ctrl_pkg.all;

 entity spec_adc_top is
  generic (
-    g_WRPC_INITF : string  := "../../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram";
+    g_WRPC_INITF    : string  := "../../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram";
    g_MT_CPU0_INITF : string  := "../../../../software/firmware/adc/wrtd-rt-adc.bram";
    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
    -- changed to non-zero in the instantiation of the top level DUT in the
    -- testbench. Its purpose is to reduce some internal counters/timeouts
    -- to speed up simulations.
-    g_SIMULATION     : integer := 0);
+    g_SIMULATION    : integer := 0);
  port (
    -- Reset button
    button1_n_i : in  std_logic;
@@ -332,8 +331,7 @@ architecture arch of spec_adc_top is
  constant c_FMC_MUX_MASK : t_wishbone_address_array(0 downto 0) :=
    (0 => x"10000000");

-
-  constant c_mt_config : t_mt_config :=
+  constant c_MT_CONFIG : t_mt_config :=
    (
      app_id                        => x"115790d1",
      cpu_count                     => 1,