[hdl] update SPEC ADC testbench to work with the convention

b4b2b1e4 · Dimitris Lampridis · 6118f656 · b4b2b1e4 · b4b2b1e4 · b4b2b1e4
Commit b4b2b1e4 authored Jul 25, 2019 by Dimitris Lampridis
5 changed files
--- a/hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
+++ b/hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
@@ -14,8 +14,6 @@ syn_tool    = "ise"
 if locals().get('fetchto', None) is None:
    fetchto = "../../../dependencies"

-ctrls = ["bank3_64b_32b"]
-
 files = [
    "wrtd_ref_spec150t_adc.ucf",
    "buildinfo_pkg.vhd",
@@ -36,3 +34,5 @@ except:
  pass

 syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
+
+ctrls = ["bank3_64b_32b"]
--- a/hdl/testbench/wrtd_ref_spec150t_adc/.gitignore
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/.gitignore
@@ -4,3 +4,4 @@ Makefile
 modelsim.ini
 transcript*
 *.wlf
+buildinfo_pkg.vhd
--- a/hdl/testbench/wrtd_ref_spec150t_adc/Manifest.py
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/Manifest.py
 board      = "spec"
 sim_tool   = "modelsim"
-top_module = "main"
+sim_top    = "main"
 action     = "simulation"
 target     = "xilinx"
 syn_device = "xc6slx150t"
 vcom_opt   = "-93 -mixedsvvh"

-fetchto    = "../../../dependencies"
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+    fetchto = "../../../dependencies"

 sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware"

-ctrls = ["bank3_64b_32b"]
-
 include_dirs = [
    "../include",
    fetchto + "/gn4124-core/hdl/gn4124core/sim/gn4124_bfm",
@@ -31,3 +32,11 @@ modules = {
        "../../top/wrtd_ref_spec150t_adc",
    ],
 }
+
+ctrls = ["bank3_64b_32b"]
+
+# Do not fail during hdlmake fetch
+try:
+  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
+except:
+  pass
--- a/hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
@@ -291,16 +291,16 @@ module dut_env

   initial begin
      // Skip WR SoftPLL lock
-      force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.WRPC.
-        U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
+      force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
+        WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
      // Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
-      force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
+      force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
        WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
          multiplier.D1.OPMODE_dly = 0;
-      force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
+      force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
        WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
          multiplier.D2.OPMODE_dly = 0;
-      force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
+      force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
        WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
          multiplier.D3.OPMODE_dly = 0;
   end // initial begin

--- a/hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
+++ b/hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
@@ -220,7 +220,7 @@ architecture arch of wrtd_ref_spec150t_adc is
  constant c_WB_SLAVE_FMC_ADC  : integer := 1;
  constant c_WB_SLAVE_MT       : integer := 2;

-  -- Convertion metadata base address
+  -- Convention metadata base address
  constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";

  -- Primary wishbone crossbar layout