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White Rabbit Trigger Distribution
Commits
c2a0c4e2
Commit
c2a0c4e2
authored
Jul 30, 2019
by
Dimitris Lampridis
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[hdl] switch to FMC-ADC with Cheby CSR and proper constraints for multi-bit CDC
parent
4e417045
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4 changed files
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24 additions
and
11 deletions
+24
-11
fmc-adc-100m14b4cha-gw
dependencies/fmc-adc-100m14b4cha-gw
+1
-1
general-cores
dependencies/general-cores
+1
-1
wrtd_ref_spec150t_adc.ucf
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
+14
-1
main.sv
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
+8
-8
No files found.
fmc-adc-100m14b4cha-gw
@
3501364d
Subproject commit
1e0e561f4902940a0b3ec85bdc863ac92cc650da
Subproject commit
3501364d856e1ee57591fcaafafff9ebe8ef229f
general-cores
@
eaacde90
Subproject commit
5dde6da558083312cfd98d721e14b36a03e2a0bc
Subproject commit
eaacde903ef842af456c867947a0f1005f8bb4f3
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @
c2a0c4e2
...
@@ -289,6 +289,16 @@ TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DAT
...
@@ -289,6 +289,16 @@ TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DAT
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_wr (3x multicycle)
NET "*/gc_sync_word_wr_data[*]" TNM = FFS "sync_word";
TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
TIMESPEC TS_sys_62m5_sync_word = FROM sync_word TO sys_clk_62_5 48ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_word = FROM sync_word TO clk_125m_pllref 24ns DATAPATHONLY;
TIMESPEC TS_dmtd_sync_word = FROM sync_word TO clk_dmtd 48ns DATAPATHONLY;
TIMESPEC TS_phy_sync_word = FROM sync_word TO phy_clk 24ns DATAPATHONLY;
# DDR (bank 3)
# DDR (bank 3)
NET "ddr0_rzq_b" LOC = K7;
NET "ddr0_rzq_b" LOC = K7;
NET "ddr0_we_n_o" LOC = H2;
NET "ddr0_we_n_o" LOC = H2;
...
@@ -496,7 +506,7 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
...
@@ -496,7 +506,7 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
# Cross-clock domain sync
# Cross-clock domain sync
#----------------------------------------
#----------------------------------------
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk"
TNM_NET = fs_clk;
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr0_bank3_clk;
NET "*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr0_bank3_clk;
...
@@ -514,6 +524,9 @@ TIMEGRP "fmc0_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
...
@@ -514,6 +524,9 @@ TIMEGRP "fmc0_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr0_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr0_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc0_adc_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc0_adc_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
TIMESPEC TS_adc_sync_word = FROM sync_word TO fs_clk 40ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# and data across implementations. Note that due to RLOC constraints in the
...
...
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @
c2a0c4e2
...
@@ -76,10 +76,10 @@ module main;
...
@@ -76,10 +76,10 @@ module main;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES
,
'h00
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES
,
'h00
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES
,
'h40
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES
,
'h40
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_SHOTS
,
'h01
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_SHOTS
,
'h01
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_
GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_
CALIB
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_
GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_
CALIB
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_
GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_
CALIB
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_
GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_
CALIB
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_SAT
,
'h7fff
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_SAT
,
'h7fff
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_SAT
,
'h7fff
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_SAT
,
'h7fff
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_SAT
,
'h7fff
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_SAT
,
'h7fff
)
;
...
@@ -111,10 +111,10 @@ module main;
...
@@ -111,10 +111,10 @@ module main;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES
,
'h00
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES
,
'h00
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES
,
'h40
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES
,
'h40
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_SHOTS
,
'h01
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_SHOTS
,
'h01
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_
GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_
CALIB
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_
GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_
CALIB
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_
GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_
CALIB
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_
GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_
CALIB
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_SAT
,
'h7fff
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_SAT
,
'h7fff
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_SAT
,
'h7fff
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_SAT
,
'h7fff
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_SAT
,
'h7fff
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_SAT
,
'h7fff
)
;
...
...
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