Commit daee642c authored by Tristan Gingold's avatar Tristan Gingold

tb: add very simple fd monitor.

parent c283c9b9
......@@ -159,14 +159,8 @@ module simple_fdelay_mon
input [3:0] pulse
);
task display_pulse ();
string tmp;
tmp = $sformatf("[FDEL] Pulse: len=%x, val=%x, out=%x", len, val, pulse);
$display (tmp);
endtask // display_pulse
always@(posedge pulse) begin
display_pulse();
always@pulse begin
$display("[FDEL] <%t> Pulse: len=%x, val=%x, out=%x", $time, len, val, pulse);
end
endmodule // simple_fdelay_mon
......@@ -288,7 +282,6 @@ module main;
// WRTD receiver (Fine Delay)
//
/* -----\/----- EXCLUDED -----\/-----
simple_fdelay_mon
FDL
(
......@@ -296,7 +289,6 @@ module main;
.val (fdl_val),
.pulse (fdl_pulse)
);
-----/\----- EXCLUDED -----/\----- */
svec_list_top #
(
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment