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White Rabbit Trigger Distribution
Commit fd2d1887 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] update SPEC template

parent 6d5d6061
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Showing with 116 additions and 488 deletions
fmc-adc-100m14b4cha-gw @ bb2303fc
Subproject commit 3501364d856e1ee57591fcaafafff9ebe8ef229f
Subproject commit bb2303fc1a28758fc726e86c1491a292588e86ab
general-cores @ 14e96565
Subproject commit eaacde903ef842af456c867947a0f1005f8bb4f3
Subproject commit 14e96565da18eee7960c69f927edc31e820a2e3c
gn4124-core @ d46281e6
Subproject commit 2d01bc96a015a14ae90a449a52b86105c5c99b75
Subproject commit d46281e65b39f1c3fe25686b3d14dadbc854438f
spec @ 7ebae5ae
Subproject commit ff41468d28db8a6609f0d8aa26f6f6c160635661
Subproject commit 7ebae5ae42c88abadec0b03b8634ba822d5b6d6a
hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
View file @ fd2d1887
......@@ -35,4 +35,6 @@ except:
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec_template_ucf = ['wr', 'ddr3', 'onewire', 'spi']
ctrls = ["bank3_64b_32b"]
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @ fd2d1887
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "gn_rst_n_i" LOC = N20;
NET "gn_p2l_clk_n_i" LOC = M19;
NET "gn_p2l_clk_p_i" LOC = M20;
NET "gn_p2l_rdy_o" LOC = J16;
NET "gn_p2l_dframe_i" LOC = J22;
NET "gn_p2l_valid_i" LOC = L19;
NET "gn_p2l_data_i[15]" LOC = H19;
NET "gn_p2l_data_i[14]" LOC = F21;
NET "gn_p2l_data_i[13]" LOC = F22;
NET "gn_p2l_data_i[12]" LOC = E20;
NET "gn_p2l_data_i[11]" LOC = E22;
NET "gn_p2l_data_i[10]" LOC = J19;
NET "gn_p2l_data_i[9]" LOC = H20;
NET "gn_p2l_data_i[8]" LOC = K19;
NET "gn_p2l_data_i[7]" LOC = K18;
NET "gn_p2l_data_i[6]" LOC = G20;
NET "gn_p2l_data_i[5]" LOC = G22;
NET "gn_p2l_data_i[4]" LOC = K17;
NET "gn_p2l_data_i[3]" LOC = L17;
NET "gn_p2l_data_i[2]" LOC = H21;
NET "gn_p2l_data_i[1]" LOC = H22;
NET "gn_p2l_data_i[0]" LOC = K20;
NET "gn_p_wr_req_i[1]" LOC = M21;
NET "gn_p_wr_req_i[0]" LOC = M22;
NET "gn_p_wr_rdy_o[1]" LOC = K16;
NET "gn_p_wr_rdy_o[0]" LOC = L15;
NET "gn_rx_error_o" LOC = J17;
NET "gn_l2p_clk_n_o" LOC = K22;
NET "gn_l2p_clk_p_o" LOC = K21;
NET "gn_l2p_dframe_o" LOC = U22;
NET "gn_l2p_valid_o" LOC = T18;
NET "gn_l2p_edb_o" LOC = U20;
NET "gn_l2p_data_o[15]" LOC = Y21;
NET "gn_l2p_data_o[14]" LOC = W20;
NET "gn_l2p_data_o[13]" LOC = V20;
NET "gn_l2p_data_o[12]" LOC = V22;
NET "gn_l2p_data_o[11]" LOC = T19;
NET "gn_l2p_data_o[10]" LOC = T21;
NET "gn_l2p_data_o[9]" LOC = R22;
NET "gn_l2p_data_o[8]" LOC = P22;
NET "gn_l2p_data_o[7]" LOC = Y22;
NET "gn_l2p_data_o[6]" LOC = W22;
NET "gn_l2p_data_o[5]" LOC = V19;
NET "gn_l2p_data_o[4]" LOC = V21;
NET "gn_l2p_data_o[3]" LOC = T20;
NET "gn_l2p_data_o[2]" LOC = P18;
NET "gn_l2p_data_o[1]" LOC = P21;
NET "gn_l2p_data_o[0]" LOC = P16;
NET "gn_l2p_rdy_i" LOC = U19;
NET "gn_l_wr_rdy_i[1]" LOC = T22;
NET "gn_l_wr_rdy_i[0]" LOC = R20;
NET "gn_p_rd_d_rdy_i[1]" LOC = P19;
NET "gn_p_rd_d_rdy_i[0]" LOC = N16;
NET "gn_tx_error_i" LOC = M17;
NET "gn_vc_rdy_i[1]" LOC = B22;
NET "gn_vc_rdy_i[0]" LOC = B21;
NET "gn_gpio_b[1]" LOC = AB19;
NET "gn_gpio_b[0]" LOC = U16;
NET "gn_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_?_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clk_?_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error_i" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_gpio_b[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_rxn_i" LOC = C15;
NET "sfp_rxp_i" LOC = D15;
NET "sfp_txn_o" LOC = A16;
NET "sfp_txp_o" LOC = B16;
NET "sfp_los_i" LOC = D18;
NET "sfp_mod_def0_i" LOC = G15;
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_fault_i" LOC = B18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "pll25dac_sync_n_o" LOC = A3;
NET "pll20dac_sync_n_o" LOC = B3;
NET "plldac_din_o" LOC = C4;
NET "plldac_sclk_o" LOC = A4;
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o" LOC = AA3;
NET "spi_sclk_o" LOC = Y20;
NET "spi_mosi_o" LOC = AB20;
NET "spi_miso_i" LOC = AA20;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS25";
NET "spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "spi_miso_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = B2;
NET "uart_rxd_i" LOC = A2;
NET "uart_txd_o" IOSTANDARD = "LVCMOS25";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer + unique ID
#----------------------------------------
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier front panel LEDs
#----------------------------------------
NET "led_sfp_red_o" LOC = D5;
NET "led_sfp_green_o" LOC = E5;
NET "led_sfp_red_o" IOSTANDARD = "LVCMOS25";
NET "led_sfp_green_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[0]" LOC = P5;
NET "pcbrev_i[1]" LOC = P4;
NET "pcbrev_i[2]" LOC = AA2;
NET "pcbrev_i[3]" LOC = AA1;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# PCB Buttons and LEDs
#----------------------------------------
NET "button1_n_i" LOC = C22;
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
NET "button1_n_i" IOSTANDARD = "LVCMOS18";
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_scl_b" LOC = F7;
NET "fmc0_sda_b" LOC = F8;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# All input clocks
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_in;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_in;
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_pllref_in" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp;
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "gn_p2l_clk_p_i" TNM_NET = "p2l_clk";
NET "gn_p2l_clk_n_i" TNM_NET = "p2l_clk";
TIMESPEC TS_p2l_clk = PERIOD "p2l_clk" 5 ns HIGH 50%;
#----------------------------------------
# WR DMTD tweaks
#----------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# GN4124
NET "gn_rst_n_i" TIG;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "cmp_spec_template_wr/clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "cmp_spec_template_wr/clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "cmp_spec_template_wr/clk_ddr_333m" TNM_NET = ddr_clk;
NET "*cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "*cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_clk;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_wr (3x multicycle)
NET "*/gc_sync_word_wr_data[*]" TNM = FFS "sync_word";
#TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
TIMESPEC TS_sys_62m5_sync_word = FROM sync_word TO sys_clk_62_5 48ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_word = FROM sync_word TO clk_125m_pllref 24ns DATAPATHONLY;
#TIMESPEC TS_dmtd_sync_word = FROM sync_word TO clk_dmtd 48ns DATAPATHONLY;
#TIMESPEC TS_phy_sync_word = FROM sync_word TO phy_clk 24ns DATAPATHONLY;
# DDR (bank 3)
NET "ddr0_rzq_b" LOC = K7;
NET "ddr0_we_n_o" LOC = H2;
NET "ddr0_udqs_p_b" LOC = V2;
NET "ddr0_udqs_n_b" LOC = V1;
NET "ddr0_udm_o" LOC = P3;
NET "ddr0_reset_n_o" LOC = E3;
NET "ddr0_ras_n_o" LOC = M5;
NET "ddr0_odt_o" LOC = L6;
NET "ddr0_ldqs_p_b" LOC = N3;
NET "ddr0_ldqs_n_b" LOC = N1;
NET "ddr0_ldm_o" LOC = N4;
NET "ddr0_cke_o" LOC = F2;
NET "ddr0_ck_p_o" LOC = K4;
NET "ddr0_ck_n_o" LOC = K3;
NET "ddr0_cas_n_o" LOC = M4;
NET "ddr0_dq_b[15]" LOC = Y1;
NET "ddr0_dq_b[14]" LOC = Y2;
NET "ddr0_dq_b[13]" LOC = W1;
NET "ddr0_dq_b[12]" LOC = W3;
NET "ddr0_dq_b[11]" LOC = U1;
NET "ddr0_dq_b[10]" LOC = U3;
NET "ddr0_dq_b[9]" LOC = T1;
NET "ddr0_dq_b[8]" LOC = T2;
NET "ddr0_dq_b[7]" LOC = M1;
NET "ddr0_dq_b[6]" LOC = M2;
NET "ddr0_dq_b[5]" LOC = L1;
NET "ddr0_dq_b[4]" LOC = L3;
NET "ddr0_dq_b[3]" LOC = P1;
NET "ddr0_dq_b[2]" LOC = P2;
NET "ddr0_dq_b[1]" LOC = R1;
NET "ddr0_dq_b[0]" LOC = R3;
NET "ddr0_ba_o[2]" LOC = H1;
NET "ddr0_ba_o[1]" LOC = J1;
NET "ddr0_ba_o[0]" LOC = J3;
NET "ddr0_a_o[13]" LOC = J6;
NET "ddr0_a_o[12]" LOC = F1;
NET "ddr0_a_o[11]" LOC = E1;
NET "ddr0_a_o[10]" LOC = J4;
NET "ddr0_a_o[9]" LOC = G1;
NET "ddr0_a_o[8]" LOC = G3;
NET "ddr0_a_o[7]" LOC = K6;
NET "ddr0_a_o[6]" LOC = L4;
NET "ddr0_a_o[5]" LOC = M3;
NET "ddr0_a_o[4]" LOC = H3;
NET "ddr0_a_o[3]" LOC = M6;
NET "ddr0_a_o[2]" LOC = K5;
NET "ddr0_a_o[1]" LOC = K1;
NET "ddr0_a_o[0]" LOC = K2;
# DDR IO standards and terminations
NET "ddr0_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr0_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IN_TERM = NONE;
NET "ddr0_ldqs_p_b" IN_TERM = NONE;
NET "ddr0_ldqs_n_b" IN_TERM = NONE;
NET "ddr0_udqs_p_b" IN_TERM = NONE;
NET "ddr0_udqs_n_b" IN_TERM = NONE;
#----------------------------------------
# FMC slot
......@@ -462,7 +95,28 @@ NET "fmc0_adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
# PCB LEDs
#----------------------------------------
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
INST "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X68Y2;
#----------------------------------------
# IOB exceptions
#----------------------------------------
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
......@@ -471,50 +125,22 @@ INST "cmp0_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FA
#----------------------------------------
# Clocks
#----------------------------------------
NET "fmc0_adc_dco_n_i" TNM_NET = fmc0_adc_dco_n_i;
TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "*cmp_ddr_ctrl_bank3/*/c?_pll_lock" TIG;
NET "*cmp_ddr_ctrl_bank3/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "*cmp_ddr_ctrl_bank3/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#ERR NET "*cmp_ddr_ctrl_bank3/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset to DDR controller
NET "cmp_spec_template_wr/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
NET "fmc0_adc_dco_p_i" TNM_NET = "fmc0_adc_dco";
NET "fmc0_adc_dco_n_i" TNM_NET = "fmc0_adc_dco";
TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco" 2.5 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
TIMEGRP "fmc_adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk";
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
TIMESPEC TS_adc_sync_ffs = FROM fs_clk TO "fmc_adc_sync_ffs" TIG;
TIMESPEC TS_adc_sync_ffs = FROM fs_clk TO "fmc_adc_sync_ffs" TIG;
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
TIMEGRP "fmc_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc_adc_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc_adc_sync_reg" 10ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
TIMESPEC TS_adc_sync_word = FROM sync_word TO fs_clk 30ns DATAPATHONLY;
TIMESPEC TS_adc_sync_word = FROM sync_word TO fs_clk 30ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
INST "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X68Y2;
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @ fd2d1887
......@@ -87,15 +87,15 @@ module dut_env
.clk_125m_pllref_n_i (~clk_125m_pll),
.clk_125m_gtp_n_i (clk_125m_gtp),
.clk_125m_gtp_p_i (~clk_125m_gtp),
.pll25dac_sync_n_o (),
.pll20dac_sync_n_o (),
.pll25dac_cs_n_o (),
.pll20dac_cs_n_o (),
.plldac_din_o (),
.plldac_sclk_o (),
.led_sfp_red_o (),
.led_sfp_green_o (),
.led_act_o (),
.led_link_o (),
.aux_leds_o (),
.pcbrev_i (4'b0),
.carrier_onewire_b (),
.onewire_b (),
.sfp_txp_o (sfp_txp_o),
.sfp_txn_o (sfp_txn_o),
.sfp_rxp_i (sfp_rxp_i),
......@@ -135,24 +135,24 @@ module dut_env
.gn_tx_error_i (i_gn4124.tx_error),
.gn_vc_rdy_i (i_gn4124.vc_rdy),
.gn_gpio_b (),
.ddr0_a_o (ddr_a),
.ddr0_ba_o (ddr_ba),
.ddr0_cas_n_o (ddr_cas_n),
.ddr0_ck_n_o (ddr_ck_n),
.ddr0_ck_p_o (ddr_ck_p),
.ddr0_cke_o (ddr_cke),
.ddr0_dq_b (ddr_dq),
.ddr0_ldm_o (ddr_dm[0]),
.ddr0_ldqs_n_b (ddr_dqs_n[0]),
.ddr0_ldqs_p_b (ddr_dqs_p[0]),
.ddr0_odt_o (ddr_odt),
.ddr0_ras_n_o (ddr_ras_n),
.ddr0_reset_n_o (ddr_reset_n),
.ddr0_rzq_b (ddr_rzq),
.ddr0_udm_o (ddr_dm[1]),
.ddr0_udqs_n_b (ddr_dqs_n[1]),
.ddr0_udqs_p_b (ddr_dqs_p[1]),
.ddr0_we_n_o (ddr_we_n),
.ddr_a_o (ddr_a),
.ddr_ba_o (ddr_ba),
.ddr_cas_n_o (ddr_cas_n),
.ddr_ck_n_o (ddr_ck_n),
.ddr_ck_p_o (ddr_ck_p),
.ddr_cke_o (ddr_cke),
.ddr_dq_b (ddr_dq),
.ddr_ldm_o (ddr_dm[0]),
.ddr_ldqs_n_b (ddr_dqs_n[0]),
.ddr_ldqs_p_b (ddr_dqs_p[0]),
.ddr_odt_o (ddr_odt),
.ddr_ras_n_o (ddr_ras_n),
.ddr_reset_n_o (ddr_reset_n),
.ddr_rzq_b (ddr_rzq),
.ddr_udm_o (ddr_dm[1]),
.ddr_udqs_n_b (ddr_dqs_n[1]),
.ddr_udqs_p_b (ddr_dqs_p[1]),
.ddr_we_n_o (ddr_we_n),
.fmc0_adc_ext_trigger_p_i (ext_trigger_i),
.fmc0_adc_ext_trigger_n_i (~ext_trigger_i),
.fmc0_adc_dco_p_i (clk_400m_adc),
......@@ -291,16 +291,16 @@ module dut_env
initial begin
// Skip WR SoftPLL lock
force DUT.cmp_spec_template_wr.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
force DUT.inst_spec_template.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.cmp_spec_template_wr.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
force DUT.inst_spec_template.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT.cmp_spec_template_wr.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
force DUT.inst_spec_template.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT.cmp_spec_template_wr.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
force DUT.inst_spec_template.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end // initial begin
......
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @ fd2d1887
......@@ -168,7 +168,7 @@ module main;
accA.write('h2000, 'h00000001); // xfer start
wait (DUTA.DUT.cmp_spec_template_wr.irqs[0] == 1);
wait (DUTA.DUT.inst_spec_template.irqs[0] == 1);
$display("[DUT:A] <%t> END DMA 1", $realtime);
end
......@@ -194,7 +194,7 @@ module main;
accB.write('h2000, 'h00000001); // xfer start
wait (DUTB.DUT.cmp_spec_template_wr.irqs[0] == 1);
wait (DUTB.DUT.inst_spec_template.irqs[0] == 1);
$display("[DUT:B] <%t> END DMA 1", $realtime);
end
......
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @ fd2d1887
......@@ -61,14 +61,14 @@ entity wrtd_ref_spec150t_adc is
clk_125m_gtp_p_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n_o : out std_logic; -- 25MHz VCXO
pll20dac_sync_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
pll25dac_cs_n_o : out std_logic; -- 25MHz VCXO
pll20dac_cs_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
-- Carrier front panel LEDs
led_sfp_red_o : out std_logic;
led_sfp_green_o : out std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
-- Auxiliary pins
aux_leds_o : out std_logic_vector(3 downto 0);
......@@ -77,7 +77,7 @@ entity wrtd_ref_spec150t_adc is
pcbrev_i : in std_logic_vector(3 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
carrier_onewire_b : inout std_logic;
onewire_b : inout std_logic;
-- SFP
sfp_txp_o : out std_logic;
......@@ -134,24 +134,24 @@ entity wrtd_ref_spec150t_adc is
------------------------------------------
-- DDR (bank 3)
------------------------------------------
ddr0_a_o : out std_logic_vector(13 downto 0);
ddr0_ba_o : out std_logic_vector(2 downto 0);
ddr0_cas_n_o : out std_logic;
ddr0_ck_n_o : out std_logic;
ddr0_ck_p_o : out std_logic;
ddr0_cke_o : out std_logic;
ddr0_dq_b : inout std_logic_vector(15 downto 0);
ddr0_ldm_o : out std_logic;
ddr0_ldqs_n_b : inout std_logic;
ddr0_ldqs_p_b : inout std_logic;
ddr0_odt_o : out std_logic;
ddr0_ras_n_o : out std_logic;
ddr0_reset_n_o : out std_logic;
ddr0_rzq_b : inout std_logic;
ddr0_udm_o : out std_logic;
ddr0_udqs_n_b : inout std_logic;
ddr0_udqs_p_b : inout std_logic;
ddr0_we_n_o : out std_logic;
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic;
------------------------------------------
-- FMC slots
......@@ -340,7 +340,7 @@ architecture arch of wrtd_ref_spec150t_adc is
signal fmc0_wb_ddr_out : t_wishbone_master_data64_out;
-- Interrupts and status
signal ddr0_wr_fifo_empty : std_logic;
signal ddr_wr_fifo_empty : std_logic;
signal fmc0_irq : std_logic;
signal irq_vector : std_logic_vector(4 downto 0);
signal gn4124_access : std_logic;
......@@ -360,7 +360,7 @@ begin -- architecture arch
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
cmp_spec_template_wr : entity work.spec_template_wr
inst_spec_template : entity work.spec_template_wr
generic map (
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
......@@ -400,14 +400,14 @@ begin -- architecture arch
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => carrier_onewire_b,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_sfp_red_o,
led_link_o => led_sfp_green_o,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
......@@ -416,8 +416,8 @@ begin -- architecture arch
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_sync_n_o,
pll20dac_cs_n_o => pll20dac_sync_n_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
......@@ -429,29 +429,29 @@ begin -- architecture arch
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr_a_o => ddr0_a_o,
ddr_ba_o => ddr0_ba_o,
ddr_cas_n_o => ddr0_cas_n_o,
ddr_ck_n_o => ddr0_ck_n_o,
ddr_ck_p_o => ddr0_ck_p_o,
ddr_cke_o => ddr0_cke_o,
ddr_dq_b => ddr0_dq_b,
ddr_ldm_o => ddr0_ldm_o,
ddr_ldqs_n_b => ddr0_ldqs_n_b,
ddr_ldqs_p_b => ddr0_ldqs_p_b,
ddr_odt_o => ddr0_odt_o,
ddr_ras_n_o => ddr0_ras_n_o,
ddr_reset_n_o => ddr0_reset_n_o,
ddr_rzq_b => ddr0_rzq_b,
ddr_udm_o => ddr0_udm_o,
ddr_udqs_n_b => ddr0_udqs_n_b,
ddr_udqs_p_b => ddr0_udqs_p_b,
ddr_we_n_o => ddr0_we_n_o,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_ref_125m,
ddr_dma_rst_n_i => rst_ref_125m_n,
ddr_dma_wb_i => fmc0_wb_ddr_out,
ddr_dma_wb_o => fmc0_wb_ddr_in,
ddr_wr_fifo_empty_o => ddr0_wr_fifo_empty,
ddr_wr_fifo_empty_o => ddr_wr_fifo_empty,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => clk_ref_125m,
......@@ -616,7 +616,7 @@ begin -- architecture arch
wb_ddr_master_i => fmc0_wb_ddr_in,
wb_ddr_master_o => fmc0_wb_ddr_out,
ddr_wr_fifo_empty_i => ddr0_wr_fifo_empty,
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty,
trig_irq_o => open,
acq_end_irq_o => open,
eic_irq_o => fmc0_irq,
......
software/firmware/adc/Makefile
View file @ fd2d1887
......@@ -10,7 +10,7 @@ EXTRA2_CFLAGS += # To be set by user on make line
EXTRA_CFLAGS += $(EXTRA2_CFLAGS)
EXTRA_CFLAGS += -I$(CUR_DIR)/../../include
EXTRA_CFLAGS += -I$(CUR_DIR)/../common
EXTRA_CFLAGS += -I$(WRTD_DEP_FMC_ADC)/hdl/rtl/wb_gen
EXTRA_CFLAGS += -I$(WRTD_DEP_FMC_ADC)/software/include/hw
all:
......
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