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White Rabbit Trigger Distribution
Commits
fd2d1887
Commit
fd2d1887
authored
Aug 02, 2019
by
Dimitris Lampridis
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[hdl] update SPEC template
parent
6d5d6061
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10 changed files
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116 additions
and
488 deletions
+116
-488
fmc-adc-100m14b4cha-gw
dependencies/fmc-adc-100m14b4cha-gw
+1
-1
general-cores
dependencies/general-cores
+1
-1
gn4124-core
dependencies/gn4124-core
+1
-1
spec
dependencies/spec
+1
-1
Manifest.py
hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
+2
-0
wrtd_ref_spec150t_adc.ucf
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
+28
-402
dut_env.sv
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
+27
-27
main.sv
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
+2
-2
wrtd_ref_spec150t_adc.vhd
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
+52
-52
Makefile
software/firmware/adc/Makefile
+1
-1
No files found.
fmc-adc-100m14b4cha-gw
@
bb2303fc
Subproject commit
3501364d856e1ee57591fcaafafff9ebe8ef229f
Subproject commit
bb2303fc1a28758fc726e86c1491a292588e86ab
general-cores
@
14e96565
Subproject commit
eaacde903ef842af456c867947a0f1005f8bb4f3
Subproject commit
14e96565da18eee7960c69f927edc31e820a2e3c
gn4124-core
@
d46281e6
Subproject commit
2d01bc96a015a14ae90a449a52b86105c5c99b75
Subproject commit
d46281e65b39f1c3fe25686b3d14dadbc854438f
spec
@
7ebae5ae
Subproject commit
ff41468d28db8a6609f0d8aa26f6f6c160635661
Subproject commit
7ebae5ae42c88abadec0b03b8634ba822d5b6d6a
hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
View file @
fd2d1887
...
@@ -35,4 +35,6 @@ except:
...
@@ -35,4 +35,6 @@ except:
syn_post_project_cmd
=
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
syn_post_project_cmd
=
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec_template_ucf
=
[
'wr'
,
'ddr3'
,
'onewire'
,
'spi'
]
ctrls
=
[
"bank3_64b_32b"
]
ctrls
=
[
"bank3_64b_32b"
]
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @
fd2d1887
This diff is collapsed.
Click to expand it.
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @
fd2d1887
...
@@ -87,15 +87,15 @@ module dut_env
...
@@ -87,15 +87,15 @@ module dut_env
.
clk_125m_pllref_n_i
(
~
clk_125m_pll
)
,
.
clk_125m_pllref_n_i
(
~
clk_125m_pll
)
,
.
clk_125m_gtp_n_i
(
clk_125m_gtp
)
,
.
clk_125m_gtp_n_i
(
clk_125m_gtp
)
,
.
clk_125m_gtp_p_i
(
~
clk_125m_gtp
)
,
.
clk_125m_gtp_p_i
(
~
clk_125m_gtp
)
,
.
pll25dac_
sync_n_o
()
,
.
pll25dac_
cs_n_o
()
,
.
pll20dac_
sync_n_o
()
,
.
pll20dac_
cs_n_o
()
,
.
plldac_din_o
()
,
.
plldac_din_o
()
,
.
plldac_sclk_o
()
,
.
plldac_sclk_o
()
,
.
led_
sfp_red_o
()
,
.
led_
act_o
()
,
.
led_
sfp_green_o
()
,
.
led_
link_o
()
,
.
aux_leds_o
()
,
.
aux_leds_o
()
,
.
pcbrev_i
(
4'b0
)
,
.
pcbrev_i
(
4'b0
)
,
.
carrier_onewire_b
()
,
.
onewire_b
()
,
.
sfp_txp_o
(
sfp_txp_o
)
,
.
sfp_txp_o
(
sfp_txp_o
)
,
.
sfp_txn_o
(
sfp_txn_o
)
,
.
sfp_txn_o
(
sfp_txn_o
)
,
.
sfp_rxp_i
(
sfp_rxp_i
)
,
.
sfp_rxp_i
(
sfp_rxp_i
)
,
...
@@ -135,24 +135,24 @@ module dut_env
...
@@ -135,24 +135,24 @@ module dut_env
.
gn_tx_error_i
(
i_gn4124
.
tx_error
)
,
.
gn_tx_error_i
(
i_gn4124
.
tx_error
)
,
.
gn_vc_rdy_i
(
i_gn4124
.
vc_rdy
)
,
.
gn_vc_rdy_i
(
i_gn4124
.
vc_rdy
)
,
.
gn_gpio_b
()
,
.
gn_gpio_b
()
,
.
ddr
0_a_o
(
ddr_a
)
,
.
ddr
_a_o
(
ddr_a
)
,
.
ddr
0_ba_o
(
ddr_ba
)
,
.
ddr
_ba_o
(
ddr_ba
)
,
.
ddr
0_cas_n_o
(
ddr_cas_n
)
,
.
ddr
_cas_n_o
(
ddr_cas_n
)
,
.
ddr
0_ck_n_o
(
ddr_ck_n
)
,
.
ddr
_ck_n_o
(
ddr_ck_n
)
,
.
ddr
0_ck_p_o
(
ddr_ck_p
)
,
.
ddr
_ck_p_o
(
ddr_ck_p
)
,
.
ddr
0_cke_o
(
ddr_cke
)
,
.
ddr
_cke_o
(
ddr_cke
)
,
.
ddr
0_dq_b
(
ddr_dq
)
,
.
ddr
_dq_b
(
ddr_dq
)
,
.
ddr
0_ldm_o
(
ddr_dm
[
0
])
,
.
ddr
_ldm_o
(
ddr_dm
[
0
])
,
.
ddr
0_ldqs_n_b
(
ddr_dqs_n
[
0
])
,
.
ddr
_ldqs_n_b
(
ddr_dqs_n
[
0
])
,
.
ddr
0_ldqs_p_b
(
ddr_dqs_p
[
0
])
,
.
ddr
_ldqs_p_b
(
ddr_dqs_p
[
0
])
,
.
ddr
0_odt_o
(
ddr_odt
)
,
.
ddr
_odt_o
(
ddr_odt
)
,
.
ddr
0_ras_n_o
(
ddr_ras_n
)
,
.
ddr
_ras_n_o
(
ddr_ras_n
)
,
.
ddr
0_reset_n_o
(
ddr_reset_n
)
,
.
ddr
_reset_n_o
(
ddr_reset_n
)
,
.
ddr
0_rzq_b
(
ddr_rzq
)
,
.
ddr
_rzq_b
(
ddr_rzq
)
,
.
ddr
0_udm_o
(
ddr_dm
[
1
])
,
.
ddr
_udm_o
(
ddr_dm
[
1
])
,
.
ddr
0_udqs_n_b
(
ddr_dqs_n
[
1
])
,
.
ddr
_udqs_n_b
(
ddr_dqs_n
[
1
])
,
.
ddr
0_udqs_p_b
(
ddr_dqs_p
[
1
])
,
.
ddr
_udqs_p_b
(
ddr_dqs_p
[
1
])
,
.
ddr
0_we_n_o
(
ddr_we_n
)
,
.
ddr
_we_n_o
(
ddr_we_n
)
,
.
fmc0_adc_ext_trigger_p_i
(
ext_trigger_i
)
,
.
fmc0_adc_ext_trigger_p_i
(
ext_trigger_i
)
,
.
fmc0_adc_ext_trigger_n_i
(
~
ext_trigger_i
)
,
.
fmc0_adc_ext_trigger_n_i
(
~
ext_trigger_i
)
,
.
fmc0_adc_dco_p_i
(
clk_400m_adc
)
,
.
fmc0_adc_dco_p_i
(
clk_400m_adc
)
,
...
@@ -291,16 +291,16 @@ module dut_env
...
@@ -291,16 +291,16 @@ module dut_env
initial
begin
initial
begin
// Skip WR SoftPLL lock
// Skip WR SoftPLL lock
force
DUT
.
cmp_spec_template_wr
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
inst_spec_template
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
U_SOFTPLL
.
U_Wrapped_Softpll
.
out_locked_o
=
3'b111
;
WRPC
.
U_SOFTPLL
.
U_Wrapped_Softpll
.
out_locked_o
=
3'b111
;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force
DUT
.
cmp_spec_template_wr
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
inst_spec_template
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D1
.
OPMODE_dly
=
0
;
multiplier
.
D1
.
OPMODE_dly
=
0
;
force
DUT
.
cmp_spec_template_wr
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
inst_spec_template
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D2
.
OPMODE_dly
=
0
;
multiplier
.
D2
.
OPMODE_dly
=
0
;
force
DUT
.
cmp_spec_template_wr
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
inst_spec_template
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D3
.
OPMODE_dly
=
0
;
multiplier
.
D3
.
OPMODE_dly
=
0
;
end
// initial begin
end
// initial begin
...
...
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @
fd2d1887
...
@@ -168,7 +168,7 @@ module main;
...
@@ -168,7 +168,7 @@ module main;
accA
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
accA
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
wait
(
DUTA
.
DUT
.
cmp_spec_template_wr
.
irqs
[
0
]
==
1
)
;
wait
(
DUTA
.
DUT
.
inst_spec_template
.
irqs
[
0
]
==
1
)
;
$
display
(
"[DUT:A] <%t> END DMA 1"
,
$
realtime
)
;
$
display
(
"[DUT:A] <%t> END DMA 1"
,
$
realtime
)
;
end
end
...
@@ -194,7 +194,7 @@ module main;
...
@@ -194,7 +194,7 @@ module main;
accB
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
accB
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
wait
(
DUTB
.
DUT
.
cmp_spec_template_wr
.
irqs
[
0
]
==
1
)
;
wait
(
DUTB
.
DUT
.
inst_spec_template
.
irqs
[
0
]
==
1
)
;
$
display
(
"[DUT:B] <%t> END DMA 1"
,
$
realtime
)
;
$
display
(
"[DUT:B] <%t> END DMA 1"
,
$
realtime
)
;
end
end
...
...
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @
fd2d1887
...
@@ -61,14 +61,14 @@ entity wrtd_ref_spec150t_adc is
...
@@ -61,14 +61,14 @@ entity wrtd_ref_spec150t_adc is
clk_125m_gtp_p_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
-- DAC interface (20MHz and 25MHz VCXO)
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_
sync
_n_o
:
out
std_logic
;
-- 25MHz VCXO
pll25dac_
cs
_n_o
:
out
std_logic
;
-- 25MHz VCXO
pll20dac_
sync
_n_o
:
out
std_logic
;
-- 20MHz VCXO
pll20dac_
cs
_n_o
:
out
std_logic
;
-- 20MHz VCXO
plldac_din_o
:
out
std_logic
;
plldac_din_o
:
out
std_logic
;
plldac_sclk_o
:
out
std_logic
;
plldac_sclk_o
:
out
std_logic
;
-- Carrier front panel LEDs
-- Carrier front panel LEDs
led_
sfp_red
_o
:
out
std_logic
;
led_
act
_o
:
out
std_logic
;
led_
sfp_green
_o
:
out
std_logic
;
led_
link
_o
:
out
std_logic
;
-- Auxiliary pins
-- Auxiliary pins
aux_leds_o
:
out
std_logic_vector
(
3
downto
0
);
aux_leds_o
:
out
std_logic_vector
(
3
downto
0
);
...
@@ -77,7 +77,7 @@ entity wrtd_ref_spec150t_adc is
...
@@ -77,7 +77,7 @@ entity wrtd_ref_spec150t_adc is
pcbrev_i
:
in
std_logic_vector
(
3
downto
0
);
pcbrev_i
:
in
std_logic_vector
(
3
downto
0
);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
carrier_
onewire_b
:
inout
std_logic
;
onewire_b
:
inout
std_logic
;
-- SFP
-- SFP
sfp_txp_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
...
@@ -134,24 +134,24 @@ entity wrtd_ref_spec150t_adc is
...
@@ -134,24 +134,24 @@ entity wrtd_ref_spec150t_adc is
------------------------------------------
------------------------------------------
-- DDR (bank 3)
-- DDR (bank 3)
------------------------------------------
------------------------------------------
ddr
0
_a_o
:
out
std_logic_vector
(
13
downto
0
);
ddr_a_o
:
out
std_logic_vector
(
13
downto
0
);
ddr
0
_ba_o
:
out
std_logic_vector
(
2
downto
0
);
ddr_ba_o
:
out
std_logic_vector
(
2
downto
0
);
ddr
0
_cas_n_o
:
out
std_logic
;
ddr_cas_n_o
:
out
std_logic
;
ddr
0
_ck_n_o
:
out
std_logic
;
ddr_ck_n_o
:
out
std_logic
;
ddr
0
_ck_p_o
:
out
std_logic
;
ddr_ck_p_o
:
out
std_logic
;
ddr
0
_cke_o
:
out
std_logic
;
ddr_cke_o
:
out
std_logic
;
ddr
0
_dq_b
:
inout
std_logic_vector
(
15
downto
0
);
ddr_dq_b
:
inout
std_logic_vector
(
15
downto
0
);
ddr
0
_ldm_o
:
out
std_logic
;
ddr_ldm_o
:
out
std_logic
;
ddr
0
_ldqs_n_b
:
inout
std_logic
;
ddr_ldqs_n_b
:
inout
std_logic
;
ddr
0
_ldqs_p_b
:
inout
std_logic
;
ddr_ldqs_p_b
:
inout
std_logic
;
ddr
0
_odt_o
:
out
std_logic
;
ddr_odt_o
:
out
std_logic
;
ddr
0
_ras_n_o
:
out
std_logic
;
ddr_ras_n_o
:
out
std_logic
;
ddr
0
_reset_n_o
:
out
std_logic
;
ddr_reset_n_o
:
out
std_logic
;
ddr
0
_rzq_b
:
inout
std_logic
;
ddr_rzq_b
:
inout
std_logic
;
ddr
0
_udm_o
:
out
std_logic
;
ddr_udm_o
:
out
std_logic
;
ddr
0
_udqs_n_b
:
inout
std_logic
;
ddr_udqs_n_b
:
inout
std_logic
;
ddr
0
_udqs_p_b
:
inout
std_logic
;
ddr_udqs_p_b
:
inout
std_logic
;
ddr
0
_we_n_o
:
out
std_logic
;
ddr_we_n_o
:
out
std_logic
;
------------------------------------------
------------------------------------------
-- FMC slots
-- FMC slots
...
@@ -340,7 +340,7 @@ architecture arch of wrtd_ref_spec150t_adc is
...
@@ -340,7 +340,7 @@ architecture arch of wrtd_ref_spec150t_adc is
signal
fmc0_wb_ddr_out
:
t_wishbone_master_data64_out
;
signal
fmc0_wb_ddr_out
:
t_wishbone_master_data64_out
;
-- Interrupts and status
-- Interrupts and status
signal
ddr
0_wr_fifo_empty
:
std_logic
;
signal
ddr
_wr_fifo_empty
:
std_logic
;
signal
fmc0_irq
:
std_logic
;
signal
fmc0_irq
:
std_logic
;
signal
irq_vector
:
std_logic_vector
(
4
downto
0
);
signal
irq_vector
:
std_logic_vector
(
4
downto
0
);
signal
gn4124_access
:
std_logic
;
signal
gn4124_access
:
std_logic
;
...
@@ -360,7 +360,7 @@ begin -- architecture arch
...
@@ -360,7 +360,7 @@ begin -- architecture arch
wb_i
=>
cnx_slave_in
(
c_WB_SLAVE_METADATA
),
wb_i
=>
cnx_slave_in
(
c_WB_SLAVE_METADATA
),
wb_o
=>
cnx_slave_out
(
c_WB_SLAVE_METADATA
));
wb_o
=>
cnx_slave_out
(
c_WB_SLAVE_METADATA
));
cmp_spec_template_wr
:
entity
work
.
spec_template_wr
inst_spec_template
:
entity
work
.
spec_template_wr
generic
map
(
generic
map
(
g_WITH_VIC
=>
TRUE
,
g_WITH_VIC
=>
TRUE
,
g_WITH_ONEWIRE
=>
FALSE
,
g_WITH_ONEWIRE
=>
FALSE
,
...
@@ -400,14 +400,14 @@ begin -- architecture arch
...
@@ -400,14 +400,14 @@ begin -- architecture arch
fmc0_scl_b
=>
fmc0_scl_b
,
fmc0_scl_b
=>
fmc0_scl_b
,
fmc0_sda_b
=>
fmc0_sda_b
,
fmc0_sda_b
=>
fmc0_sda_b
,
fmc0_prsnt_m2c_n_i
=>
fmc0_prsnt_m2c_n_i
,
fmc0_prsnt_m2c_n_i
=>
fmc0_prsnt_m2c_n_i
,
onewire_b
=>
carrier_
onewire_b
,
onewire_b
=>
onewire_b
,
spi_sclk_o
=>
spi_sclk_o
,
spi_sclk_o
=>
spi_sclk_o
,
spi_ncs_o
=>
spi_ncs_o
,
spi_ncs_o
=>
spi_ncs_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
spi_miso_i
=>
spi_miso_i
,
pcbrev_i
=>
pcbrev_i
,
pcbrev_i
=>
pcbrev_i
,
led_act_o
=>
led_
sfp_red
_o
,
led_act_o
=>
led_
act
_o
,
led_link_o
=>
led_
sfp_green
_o
,
led_link_o
=>
led_
link
_o
,
button1_i
=>
button1_n_i
,
button1_i
=>
button1_n_i
,
uart_rxd_i
=>
uart_rxd_i
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
uart_txd_o
=>
uart_txd_o
,
...
@@ -416,8 +416,8 @@ begin -- architecture arch
...
@@ -416,8 +416,8 @@ begin -- architecture arch
clk_125m_gtp_p_i
=>
clk_125m_gtp_p_i
,
clk_125m_gtp_p_i
=>
clk_125m_gtp_p_i
,
plldac_sclk_o
=>
plldac_sclk_o
,
plldac_sclk_o
=>
plldac_sclk_o
,
plldac_din_o
=>
plldac_din_o
,
plldac_din_o
=>
plldac_din_o
,
pll25dac_cs_n_o
=>
pll25dac_
sync
_n_o
,
pll25dac_cs_n_o
=>
pll25dac_
cs
_n_o
,
pll20dac_cs_n_o
=>
pll20dac_
sync
_n_o
,
pll20dac_cs_n_o
=>
pll20dac_
cs
_n_o
,
sfp_txp_o
=>
sfp_txp_o
,
sfp_txp_o
=>
sfp_txp_o
,
sfp_txn_o
=>
sfp_txn_o
,
sfp_txn_o
=>
sfp_txn_o
,
sfp_rxp_i
=>
sfp_rxp_i
,
sfp_rxp_i
=>
sfp_rxp_i
,
...
@@ -429,29 +429,29 @@ begin -- architecture arch
...
@@ -429,29 +429,29 @@ begin -- architecture arch
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_los_i
=>
sfp_los_i
,
sfp_los_i
=>
sfp_los_i
,
ddr_a_o
=>
ddr
0
_a_o
,
ddr_a_o
=>
ddr_a_o
,
ddr_ba_o
=>
ddr
0
_ba_o
,
ddr_ba_o
=>
ddr_ba_o
,
ddr_cas_n_o
=>
ddr
0
_cas_n_o
,
ddr_cas_n_o
=>
ddr_cas_n_o
,
ddr_ck_n_o
=>
ddr
0
_ck_n_o
,
ddr_ck_n_o
=>
ddr_ck_n_o
,
ddr_ck_p_o
=>
ddr
0
_ck_p_o
,
ddr_ck_p_o
=>
ddr_ck_p_o
,
ddr_cke_o
=>
ddr
0
_cke_o
,
ddr_cke_o
=>
ddr_cke_o
,
ddr_dq_b
=>
ddr
0
_dq_b
,
ddr_dq_b
=>
ddr_dq_b
,
ddr_ldm_o
=>
ddr
0
_ldm_o
,
ddr_ldm_o
=>
ddr_ldm_o
,
ddr_ldqs_n_b
=>
ddr
0
_ldqs_n_b
,
ddr_ldqs_n_b
=>
ddr_ldqs_n_b
,
ddr_ldqs_p_b
=>
ddr
0
_ldqs_p_b
,
ddr_ldqs_p_b
=>
ddr_ldqs_p_b
,
ddr_odt_o
=>
ddr
0
_odt_o
,
ddr_odt_o
=>
ddr_odt_o
,
ddr_ras_n_o
=>
ddr
0
_ras_n_o
,
ddr_ras_n_o
=>
ddr_ras_n_o
,
ddr_reset_n_o
=>
ddr
0
_reset_n_o
,
ddr_reset_n_o
=>
ddr_reset_n_o
,
ddr_rzq_b
=>
ddr
0
_rzq_b
,
ddr_rzq_b
=>
ddr_rzq_b
,
ddr_udm_o
=>
ddr
0
_udm_o
,
ddr_udm_o
=>
ddr_udm_o
,
ddr_udqs_n_b
=>
ddr
0
_udqs_n_b
,
ddr_udqs_n_b
=>
ddr_udqs_n_b
,
ddr_udqs_p_b
=>
ddr
0
_udqs_p_b
,
ddr_udqs_p_b
=>
ddr_udqs_p_b
,
ddr_we_n_o
=>
ddr
0
_we_n_o
,
ddr_we_n_o
=>
ddr_we_n_o
,
ddr_dma_clk_i
=>
clk_ref_125m
,
ddr_dma_clk_i
=>
clk_ref_125m
,
ddr_dma_rst_n_i
=>
rst_ref_125m_n
,
ddr_dma_rst_n_i
=>
rst_ref_125m_n
,
ddr_dma_wb_i
=>
fmc0_wb_ddr_out
,
ddr_dma_wb_i
=>
fmc0_wb_ddr_out
,
ddr_dma_wb_o
=>
fmc0_wb_ddr_in
,
ddr_dma_wb_o
=>
fmc0_wb_ddr_in
,
ddr_wr_fifo_empty_o
=>
ddr
0
_wr_fifo_empty
,
ddr_wr_fifo_empty_o
=>
ddr_wr_fifo_empty
,
clk_sys_62m5_o
=>
clk_sys_62m5
,
clk_sys_62m5_o
=>
clk_sys_62m5
,
rst_sys_62m5_n_o
=>
rst_sys_62m5_n
,
rst_sys_62m5_n_o
=>
rst_sys_62m5_n
,
clk_ref_125m_o
=>
clk_ref_125m
,
clk_ref_125m_o
=>
clk_ref_125m
,
...
@@ -616,7 +616,7 @@ begin -- architecture arch
...
@@ -616,7 +616,7 @@ begin -- architecture arch
wb_ddr_master_i
=>
fmc0_wb_ddr_in
,
wb_ddr_master_i
=>
fmc0_wb_ddr_in
,
wb_ddr_master_o
=>
fmc0_wb_ddr_out
,
wb_ddr_master_o
=>
fmc0_wb_ddr_out
,
ddr_wr_fifo_empty_i
=>
ddr
0
_wr_fifo_empty
,
ddr_wr_fifo_empty_i
=>
ddr_wr_fifo_empty
,
trig_irq_o
=>
open
,
trig_irq_o
=>
open
,
acq_end_irq_o
=>
open
,
acq_end_irq_o
=>
open
,
eic_irq_o
=>
fmc0_irq
,
eic_irq_o
=>
fmc0_irq
,
...
...
software/firmware/adc/Makefile
View file @
fd2d1887
...
@@ -10,7 +10,7 @@ EXTRA2_CFLAGS += # To be set by user on make line
...
@@ -10,7 +10,7 @@ EXTRA2_CFLAGS += # To be set by user on make line
EXTRA_CFLAGS
+=
$(EXTRA2_CFLAGS)
EXTRA_CFLAGS
+=
$(EXTRA2_CFLAGS)
EXTRA_CFLAGS
+=
-I
$(CUR_DIR)
/../../include
EXTRA_CFLAGS
+=
-I
$(CUR_DIR)
/../../include
EXTRA_CFLAGS
+=
-I
$(CUR_DIR)
/../common
EXTRA_CFLAGS
+=
-I
$(CUR_DIR)
/../common
EXTRA_CFLAGS
+=
-I
$(WRTD_DEP_FMC_ADC)
/
hdl/rtl/wb_gen
EXTRA_CFLAGS
+=
-I
$(WRTD_DEP_FMC_ADC)
/
software/include/hw
all
:
all
:
...
...
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