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White Rabbit Trigger Distribution
Commit fdc151d8 authored by Tristan Gingold's avatar Tristan Gingold
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Add description for fmc-adc-100m14b4cha-spec

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builder/fmc-adc-100m14b4cha-spec/config.yaml 0 → 100644
View file @ fdc151d8
repo:
"git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git"
bus:
input:
"wb_adc{n}_trigin_slave"
output:
"wb_adc{n}_trigout_slave"
builder/fmc-adc-100m14b4cha-spec/repo.txt 0 → 100644
View file @ fdc151d8
git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git
builder/fmc-adc-100m14b4cha-spec/spec-fmc0.ucf 0 → 100644
View file @ fdc151d8
# DDR (bank 3)
NET "ddr0_rzq_b" LOC = K7;
NET "ddr0_we_n_o" LOC = H2;
NET "ddr0_udqs_p_b" LOC = V2;
NET "ddr0_udqs_n_b" LOC = V1;
NET "ddr0_udm_o" LOC = P3;
NET "ddr0_reset_n_o" LOC = E3;
NET "ddr0_ras_n_o" LOC = M5;
NET "ddr0_odt_o" LOC = L6;
NET "ddr0_ldqs_p_b" LOC = N3;
NET "ddr0_ldqs_n_b" LOC = N1;
NET "ddr0_ldm_o" LOC = N4;
NET "ddr0_cke_o" LOC = F2;
NET "ddr0_ck_p_o" LOC = K4;
NET "ddr0_ck_n_o" LOC = K3;
NET "ddr0_cas_n_o" LOC = M4;
NET "ddr0_dq_b[15]" LOC = Y1;
NET "ddr0_dq_b[14]" LOC = Y2;
NET "ddr0_dq_b[13]" LOC = W1;
NET "ddr0_dq_b[12]" LOC = W3;
NET "ddr0_dq_b[11]" LOC = U1;
NET "ddr0_dq_b[10]" LOC = U3;
NET "ddr0_dq_b[9]" LOC = T1;
NET "ddr0_dq_b[8]" LOC = T2;
NET "ddr0_dq_b[7]" LOC = M1;
NET "ddr0_dq_b[6]" LOC = M2;
NET "ddr0_dq_b[5]" LOC = L1;
NET "ddr0_dq_b[4]" LOC = L3;
NET "ddr0_dq_b[3]" LOC = P1;
NET "ddr0_dq_b[2]" LOC = P2;
NET "ddr0_dq_b[1]" LOC = R1;
NET "ddr0_dq_b[0]" LOC = R3;
NET "ddr0_ba_o[2]" LOC = H1;
NET "ddr0_ba_o[1]" LOC = J1;
NET "ddr0_ba_o[0]" LOC = J3;
NET "ddr0_a_o[13]" LOC = J6;
NET "ddr0_a_o[12]" LOC = F1;
NET "ddr0_a_o[11]" LOC = E1;
NET "ddr0_a_o[10]" LOC = J4;
NET "ddr0_a_o[9]" LOC = G1;
NET "ddr0_a_o[8]" LOC = G3;
NET "ddr0_a_o[7]" LOC = K6;
NET "ddr0_a_o[6]" LOC = L4;
NET "ddr0_a_o[5]" LOC = M3;
NET "ddr0_a_o[4]" LOC = H3;
NET "ddr0_a_o[3]" LOC = M6;
NET "ddr0_a_o[2]" LOC = K5;
NET "ddr0_a_o[1]" LOC = K1;
NET "ddr0_a_o[0]" LOC = K2;
# DDR IO standards and terminations
NET "ddr0_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr0_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IN_TERM = NONE;
NET "ddr0_ldqs_p_b" IN_TERM = NONE;
NET "ddr0_ldqs_n_b" IN_TERM = NONE;
NET "ddr0_udqs_p_b" IN_TERM = NONE;
NET "ddr0_udqs_n_b" IN_TERM = NONE;
#----------------------------------------
# FMC slot
#----------------------------------------
NET "fmc0_adc_ext_trigger_n_i" LOC = AB13;
NET "fmc0_adc_ext_trigger_p_i" LOC = Y13;
# dco_p and dco_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
NET "fmc0_adc_dco_n_i" LOC = AB11;
NET "fmc0_adc_dco_p_i" LOC = Y11;
# fr_p and fr_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
NET "fmc0_adc_fr_n_i" LOC = AB12;
NET "fmc0_adc_fr_p_i" LOC = AA12;
NET "fmc0_adc_outa_n_i[0]" LOC = AB4;
NET "fmc0_adc_outa_p_i[0]" LOC = AA4;
NET "fmc0_adc_outb_n_i[0]" LOC = W11;
NET "fmc0_adc_outb_p_i[0]" LOC = V11;
NET "fmc0_adc_outa_n_i[1]" LOC = Y12;
NET "fmc0_adc_outa_p_i[1]" LOC = W12;
NET "fmc0_adc_outb_n_i[1]" LOC = AB9;
NET "fmc0_adc_outb_p_i[1]" LOC = Y9;
NET "fmc0_adc_outa_n_i[2]" LOC = AB8;
NET "fmc0_adc_outa_p_i[2]" LOC = AA8;
NET "fmc0_adc_outb_n_i[2]" LOC = AB7;
NET "fmc0_adc_outb_p_i[2]" LOC = Y7;
NET "fmc0_adc_outa_n_i[3]" LOC = V9;
NET "fmc0_adc_outa_p_i[3]" LOC = U9;
NET "fmc0_adc_outb_n_i[3]" LOC = AB6;
NET "fmc0_adc_outb_p_i[3]" LOC = AA6;
NET "fmc0_adc_spi_din_i" LOC = T15;
NET "fmc0_adc_spi_dout_o" LOC = C18;
NET "fmc0_adc_spi_sck_o" LOC = D17;
NET "fmc0_adc_spi_cs_adc_n_o" LOC = V17;
NET "fmc0_adc_spi_cs_dac1_n_o" LOC = B20;
NET "fmc0_adc_spi_cs_dac2_n_o" LOC = A20;
NET "fmc0_adc_spi_cs_dac3_n_o" LOC = C19;
NET "fmc0_adc_spi_cs_dac4_n_o" LOC = A19;
NET "fmc0_adc_gpio_dac_clr_n_o" LOC = W18;
NET "fmc0_adc_gpio_led_acq_o" LOC = W15;
NET "fmc0_adc_gpio_led_trig_o" LOC = Y16;
NET "fmc0_adc_gpio_ssr_ch1_o[0]" LOC = Y17;
NET "fmc0_adc_gpio_ssr_ch1_o[1]" LOC = AB17;
NET "fmc0_adc_gpio_ssr_ch1_o[2]" LOC = AB18;
NET "fmc0_adc_gpio_ssr_ch1_o[3]" LOC = U15;
NET "fmc0_adc_gpio_ssr_ch1_o[4]" LOC = W14;
NET "fmc0_adc_gpio_ssr_ch1_o[5]" LOC = Y14;
NET "fmc0_adc_gpio_ssr_ch1_o[6]" LOC = W17;
NET "fmc0_adc_gpio_ssr_ch2_o[0]" LOC = R11;
NET "fmc0_adc_gpio_ssr_ch2_o[1]" LOC = AB15;
NET "fmc0_adc_gpio_ssr_ch2_o[2]" LOC = R13;
NET "fmc0_adc_gpio_ssr_ch2_o[3]" LOC = T14;
NET "fmc0_adc_gpio_ssr_ch2_o[4]" LOC = V13;
NET "fmc0_adc_gpio_ssr_ch2_o[5]" LOC = AA18;
NET "fmc0_adc_gpio_ssr_ch2_o[6]" LOC = W13;
NET "fmc0_adc_gpio_ssr_ch3_o[0]" LOC = R9;
NET "fmc0_adc_gpio_ssr_ch3_o[1]" LOC = R8;
NET "fmc0_adc_gpio_ssr_ch3_o[2]" LOC = T10;
NET "fmc0_adc_gpio_ssr_ch3_o[3]" LOC = U10;
NET "fmc0_adc_gpio_ssr_ch3_o[4]" LOC = W10;
NET "fmc0_adc_gpio_ssr_ch3_o[5]" LOC = Y10;
NET "fmc0_adc_gpio_ssr_ch3_o[6]" LOC = T11;
NET "fmc0_adc_gpio_ssr_ch4_o[0]" LOC = W6;
NET "fmc0_adc_gpio_ssr_ch4_o[1]" LOC = Y6;
NET "fmc0_adc_gpio_ssr_ch4_o[2]" LOC = V7;
NET "fmc0_adc_gpio_ssr_ch4_o[3]" LOC = W8;
NET "fmc0_adc_gpio_ssr_ch4_o[4]" LOC = T8;
NET "fmc0_adc_gpio_ssr_ch4_o[5]" LOC = Y5;
NET "fmc0_adc_gpio_ssr_ch4_o[6]" LOC = U8;
NET "fmc0_adc_gpio_si570_oe_o" LOC = AB5;
NET "fmc0_adc_si570_scl_b" LOC = U12;
NET "fmc0_adc_si570_sda_b" LOC = T12;
NET "fmc0_adc_one_wire_b" LOC = Y18;
# IO standards
NET "fmc0_adc_ext_trigger_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_dco_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_fr_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_out?_?_i[*]" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_spi_din_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_dout_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_sck_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_dac?_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_acq_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_ssr_ch?_o[*]" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
#----------------------------------------
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
#----------------------------------------
# Clocks
#----------------------------------------
NET "fmc0_adc_dco_n_i" TNM_NET = fmc0_adc_dco_n_i;
TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "cmp_ddr0_ctrl_bank/*/c?_pll_lock" TIG;
NET "cmp_ddr0_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
#ERR NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#ERR NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset to DDR controller
NET "ddr0_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "cmp_ddr0_ctrl_bank/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_bank3_clk;
TIMEGRP "ddr0_clk" = "ddr0_clk_333m" "ddr0_bank3_clk";
TIMEGRP "ddr0_sync_ffs" = "sync_ffs" EXCEPT "ddr0_clk";
TIMEGRP "fmc0_adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk";
TIMESPEC TS_ddr0_sync_ffs = FROM ddr0_clk TO "ddr0_sync_ffs" TIG;
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMEGRP "ddr0_sync_reg" = "sync_reg" EXCEPT "ddr0_clk";
TIMEGRP "fmc0_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr0_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc0_adc_sync_reg" 10ns DATAPATHONLY;
builder/fmc-adc-100m14b4cha-spec/top.vhd 0 → 100644
View file @ fdc151d8
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