Golden release gateware
Release notes
- Pulse repetition with max. duty cycle of 1/200; input pulses with duty cycle >1/200 are rejected
- I2C to Wishbone bridge following the protocol defined together with ELMA
- Dedicated CONV-TTL-BLO registers (see full memory map in the HDL
guide):
- Board ID register
- CSR
- remote logic reset
- gateware version
- state of on-board switches
- state of RTM detection lines
- state of I2C watchdog timer
- Pulse and status LED control
- Remote reprogramming
Versions
Version | Release date | Description | Sources | .bin | .bit |
---|---|---|---|---|---|
v0.0 | 15-04-2014 | Pulse repetition without glitch filter and with MultiBoot | tag v0.0 in repository | golden-v0.0.bin | golden-v0.0.bit |
v0.1 | 25-04-2014 | Adds glitch filter to the pulse repetition logic | tag v0.1 in repository | golden-v0.1.bin | golden-v0.1.bit |
Documentation
- The block diagram of the logic is shown below.
* For information on the implementation of each block, consult the HDL guide:
git clone -b golden git:https://www.ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-gw.git
cd doc/hdlguide/
make
Theodor-Adrian Stana, Jan. 2014