CONV-TTL-BLO golden gateware version 0.2
Release notes
-
CHANGES IN MEMORY MAP FROM PREVIOUS VERSIONS
- the Multiboot module is now at address 0x100
- see the HDL guide for details
- Uses the converter board common gateware
- Fallback to golden gateware is now a system error
- ERR LED lit red when golden gateware is booted to
- Pulse repetition with max. frequency of 4150 Hz
- 1.2us pulse on output
- duty cycle of 1/200
- input pulses with duty cycle of more than 1/200 are rejected
- I2C to Wishbone bridge following the protocol defined together with ELMA
- Diagnostics support
- converter board ID
- gateware version
- state of on-board switches
- state of RTM detection lines
- state of I2C watchdog timer
- system errors
- remote logic reset
- line status readout from dedicated register
- Pulse and status LED control
- Remote reprogramming
- Connects VME SYSRESET signal to reset the FPGA logic
Binary files
- Binary files for remote reprogramming
- To create a complete bitstream (golden + release) for direct download to the flash, see here
Sources
- tag v0.2 in repository
- Golden gateware HDL files can be found under the golden branch.
Documentation
- Block diagram
* For the implementation of each block, consult the HDL guide
-
compile from source
git clone git:https://www.ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-gw.git cd conv-ttl-blo-gw git checkout v0.2 cd doc/hdlg/ make
Theodor-Adrian Stana, Sept. 2014