Complete status
** Date ** | ** Event ** |
---|---|
02-03-2011 | Stock manager worries about low stock of LA-TTL-BLO modules. |
01-07-2011 | Start working on project. |
20-07-2011 | Review of architecture. |
11-08-2011 | Blocking level output circuit simulated. Will be documented. |
16-08-2011 | Blocking Oscillator documentation. Brief web version available. |
23-08-2011 | Blocking Oscillator prototype made, problems integrating into CTDAH. Moving to a flyback solution. |
29-08-2011 | Blocking Oscillator Daisy-chain alternatives document. Prototype board already made, waiting for LM2733 |
12-09-2011 | Functional Specifications Draft proposed |
16-09-2011 | The flyback module that outputs the blocking signal works fine. |
20-09-2011 | Blocking standard defined. |
03-10-2011 | PF0552.104NL transformer samples were received. Pulse Converter Unit works nicely. |
04-10-2011 | Schematics draft done. See: http://svn.ohwr.org/conv-ttl-blo |
11-10-2011 | CTDAH - White Rabbit capable version up in repo (CTDAHalt). Moving to HDL. |
20-10-2011 | Second Review of architecture. Modifications accomplished to CTDAHalt |
24-10-2011 | Uploaded package containing files for schematic revision. |
03-11-2011 | Changes to the schematics upon Erik's advice. Files for schematics revision. |
10-11-2011 | Schematics design review held. Needs major revision and prototyping of a simplified output stage. |
15-11-2011 | Output stage simplified. Update of the schematics addressing the points discussed in the revision. |
21-11-2011 | Files for Schematics Revision C. |
30-11-2011 | Schematics ready for layout. Contacting with Electronics Design Office. |
12-12-2011 | Start of PCB layout. |
11-01-2012 | Received BOM from DEM. Contacted with Cristine for components. |
12-01-2012 | Added diff table for using only one RTM motherboard for both conv-ttl-blo and conv-ttl-rs485 projects. |
16-01-2012 | Added Rear Transition Module detection feature. |
19-01-2012 | PCB Review Agenda 20-01-2012 added. |
20-01-2012 | PCB Review Notes 20-01-2012 added. New wiki page: on choosing replacements for pulse transformers. |
30-01-2012 | Waiting for OS-CON availability. Added RTM pinouts and schematics for RTM Motherboard and RTM Piggyback for Blocking. |
06-02-2012 | Schematics and PCB reviewed. review06022012 |
13-02-2012 | Improving schematics and PCB based on review. review06022012comments |
21-02-2012 | Added more cores (control, multiboot and first image) to the project. See HDL blocks status Review Notes 20-02-2012](PCBN20022012-added) |
24-02-2012 | 3 prototypes ordered for 30-03-2012. |
05-04-2012 | Prototypes received. Testing HDL simple repetition code. |
19-04-2012 | DEM has not already soldered the RTM modules. One week to get them in the lab. |
20-04-2012 | Basic repetition code works from SPI flash memory. Moving to PTS and ELMA interfacing. |
08-05-2012 | WR core adapted to CONV-TTL-BLO. Bitstream has been generated. Pending the test of WR upon a set up of a WR link. |
11-05-2012 | RTMs (CONV-TTL-BLO-RTM) received from DEM. Some issues found with the lenght of the pins in 100 pin connector. |
14-05-2012 | A list of tests for CONV-TTL-BLO with the Basic Functionality Bitstream is available. |
19-06-2012 | Running some tests on image 1. I2C HDL works and moving to SPI for m25p32 HDL core. |
21-08-2012 | White Rabbit test core works! |
02-10-2012 | A lot of work put on SPI module for Flash programming. Reads and writes have been coarsed verified, still little details to give a final OK. |
03-10-2012 | Speeding up for LS1. Report of issues in CONV-TTL-BLO. Project files, schematics pdf and BOM of V2. |
10-10-2012 | Schematics design review of V2 held. |
22-10-2012 | V2 ready. Report of the design review added. Schematics , BOM and project files up in repo. |
14-11-2012 | Blocking V2 ready for review. |
21-11-2012 | Deployed a Blocking V1 in PS facilities. Source and bitstream available here |
10-12-2012 | Will build 4 V2's before building another 20 and after that 100. Ordered 25 RTM modules. |
08-01-2013 | Received 4 V2 boards. Some assembly problems on two. |
11-01-2013 | Starting transfer knowledge of the project to Thedi (Stana). |
22-01-2013 | Transfer knowledge document released. |
18-02-2013 | Order placed for 25 RTM and 27 BLO-RTMP boards. |
15-03-2013 | 25x RTMs and 27x BLO-RTMPs received |
27-03-2013 | Modifications needed for all three boards. Not expected before end of April. |
11-04-2013 | Modifications complete for front module: EDA-02446-V2-1 |
17-04-2013 | Modifications to RTMP done: EDA-02453-V1-0 |
26-04-2013 | Modifications to RTM done: EDA-02452-V2-0 |
05-06-2013 | 25 CONV-TTL-BLO boards and front panels produced |
19-06-2013 | 10 rear panels produced |
22-07-2013 | Ordered 30 ESD boxes for CONV-TTL-BLO boards |
23-07-2013 | Received the ordered ESD boxes |
30-07-2013 | Ordered 15 rear panels |
10-09-2013 | Received 15 rear panels |
11-09-2013 | Test system set up in LINAC 4 facility (see testing page for more information) |
09-10-2013 | Ordering 100 sets. |
15-11-2013 | Design review held (see design-review-2013 branch) |
20-12-2013 | Received 100 front module boards. |
09-01-2014 | Added 100 front modules to stock. |
10-01-2014 | Updated costs page. |
12-02-2014 | Received 100 produced and assembled RTMs. |
10-03-2014 | CONV-TTL-BLO now with diagnostics support. |
09-04-2014 | Gateware v2.1 released |
15-04-2014 | Gateware v2.2 released |
26-09-2014 | Gateware v3.0 released |
08-02-2016 | Reviving the test system and studying Issue 1104. |
21-06-2016 | Prototype of blocking output stage built to verify proposed modifications |
01-07-2016 | Schematics, layout and front panel modification requests sent to DEM for V3 |
05-08-2016 | EDA-02446-V3-0 Ready for release. Order placed for 3 prototypes. Components ready |
26-10-2016 | EDA-02446-V3-0 Three boards received. Outputs give unexpected overshoot. Will need a V4. |
03-02-2017 | EDA-02446-V4-0 Review held |
14-02-2017 | Updated user manual and hardware design guide for v4 boards |
8-03-2017 | v4 schematics, PCB layout, mechanical parts and manufacturing information available in EDMS |
10-03-2017 | Gateware v4.0 released |
20-03-2017 | 5 prototypes ordered of v4.0 boards, expected from 15-05-2017 |
12-06-2017 | 5 v4 prototypes have been received, small error on silkscreen leads to issue #1611 |
13-09-2017 | Schematics v4-1 released on EDMS to resolve issue #1611 |
16-10-2017 | Prototypes with new firmware successfully running on installations. Error-free since July 20th. Launch of large scale production. 460 motherboards and 405 RTM modules |
23-01-2018 | Gateware v4.1 released |
20-07-2018 | pre-series of 25 v4.1 boards have been delivered to CERN |
15-08-2018 | 405 boards of CONV-TTL-RTM-BLO, EDA-02453 v3.2 delivered at CERN |
Theodor-Adrian Stana, Carlos Gil-Soriano, Erik van der Bij, Denia Bouhired - August 23rd, 2018