Here are our current LTSpice models for the front end. If you have any
comments or observations please share them!
The model consists of three main blocks:
Transimpedence front end amplifier
Two stage signal amplifier + Pulse shaping network
Items not modeled:
Vbias + Bias resistor
ADC input (simulated with a 50 ohm resistor)
4V DC/DC converter for front end
Note - all amplifiers are run from the 4V rail, rather than the 5V USB
rail to improve noise immunity.
AC transient with 5ns rise and 34ns fall time (+/-) with 1V magnitude.
The main schematic (developed in EagleCad) is presented for design
review. If you have comments, questions or suggestions please share them
with us! Once we've finished on the schematic we'll move to finalise
the layout, and we might have another review if necessary. The BOM is
Thanks to all those who helped out by contributing comments, either
beforehand or at the physical review. Below is the completed list of
design review comments, along with the actions to be taken if considered
necessary. Note that some comments have been deleted due to duplication.
We'll be re-working the schematic over the next few days and will
archive this list once all comments are actioned.
+ Power Ratings of the components, confirmed as adequate for mA range
expected. Total power consumption < 500mA at 5V.
+ Operational Voltages of the ICs. Confirmed 3.3V/5V for all devices
with correct connections.
+ It is often seen, that sometimes there are dots missing where a
connection between wires should be. This is dangerous because you can
get problems with your PCB layout. I guess you used the 'wire' to
connect the components. But is better, maybe even necessary, to use
'net' to connect components. Done.
! IC1, IC2 – missing DC bias – operating point of existing design is at
0V where amplifiers tend to oscillate because they cannot output
voltages below 0. Rail to Rail doesn’t help much. Just connect R38 to
some 1V instead of ground. To be done, RC network impact to be
+ decouple the input of boost converter from + 5V. 1 uF is not
sufficient, it will distribute peaks in all + 5V domain. Just use some
LC filter and C>1uF at the input. Done.
+ add ferrite + decoupling for GPS. Missing capacitor at the module
+ add C for AND gate decoupling. Done.
+ Small hysteresis to the comparators to reduce glitches to be done
based on comparator datasheet. Done, values to be checked.
+ add current limiting resistors (i.e. 330Ohm) at the output of the
comparators – they produce 5V while U16 is supplied from 3.3V; Done.
+ Package replacement incomplete, all passives to be changed to 603.
-- Schematic blocks
-- Input Stage
+ Add LED for SiPM feedback. Done.
-- Amplification Stage 1
+ As you might know, the first amplification stage is the most
critical, so special care has to be taken. The 10M resistor in your
first amplifier stage is really huge. Do you really need that high gain?
Because this will introduce quite a big noise in your first stage and
this is where you want it the least. Also I strongly recommend to keep
the (all) feedbacks as short as possible in your layout. The SIG1A and
SIG1B lines should be surrounded by ground planes to provide a shielding
for the input. Input stage to be modelled in SPICE.
+ model to quantify the boundary conditions between each stage (e.g.
signal amplitude from output, frequency etc.) to be done in spice,
starting from SiPM
-- Amplification Stage 2
+ Add ferrite filter from Shaper
+ remove ferrite filter, raw 5V with decoupling should be sufficient.
+ In your shaper circuit you use the AD8602 opamp. If you experience
much noise you can also use the AD8656 if the noise or offset voltage is
a problem. The AD8656 is pin compatible with the AD8602 but has much
better noise performance and less offset voltage. We’ve decided to stick
with the AD8602 for now, but will look at this if we have noise issues
after production. No action at this stage.
-- HV PSU
+ I am really curious about how your 47V generation will do! As I
understood so far, the noise/ripple performance of the bias voltage has
a huge impact on the SiPM noise performance. So an accurate voltage is
really important but hard to realize in this voltage range. Maybe a
5V/5V DC/DC converter can be helpful to isolate your + 5V from the
Arduino and the Boost PSU control IC input. This could prevent errors in
the supply system. This comment is addressed by the earlier one where we
will add an inductor and capacitor to the DC/DC supply. Done.
+ Add feedback mechanism for 47V FSD to 3.3V ADC, via potential
divider, include reverse Zener at 3.3V to prevent pin overload!
+ 50 Ohm trace for the antenna, not required due to short trace length
– validated with our version 1 prototype; trace length <10mm. Review
only if trace >10mm
+ Pulse shaver for the PPS, to be actioned and added.
-- Accelerometer & Altimeter
+ Transistor for turn on/off as hard reset
-- Humidity & Temperature Sensor
+ Transistor for turn on/off as hard reset
-- Discriminator Threshold
! You should be cautious with your Voltage reference MAX6125. Voltage
references often cannot drive large currents (< 2mA?). So your have to
check the minimum resistances of the potentiometers. If necessary you
have to buffer the voltage reference output with an opamp (low noise -
> AD8656). Also be aware that the voltage references change its output
voltage in dependence of their load. Verified, load is ok to 1mA,
resistance is 10kOhm, so load =1mA; 40mV dropout, which we consider
acceptable. No action.
!Trigger block: JP3 should be JP8 in this comment "JP3 to short if NOT
isn't mounted, active low.". JP3 is the SPI header while JP8 is for
shorting the NOT gate. Correct. To be changed.
!You should also provide a capacitor (10nF-100nF) directly placed at
the IN+ inputs of the comparator. Done.
!Maybe they are provided somewhere else, but I do not see any
capacitors at the VCC pins of the AND gate and NOT gate! 100 nF should
do. At fast switching digital ICs, also a bigger capacitor should be
provided additionally. Done.
+ consider 555 timer(s) as an alternative architecture, to give a fixed
duration pulse. Maybe next iteration, not this time.
-- DUE Interface
! pin 20 on the DUE Shield I think should be labeled "SDA0" for the
data pin of I2C bus 0... currently reads "SDA." Done.
-- Status LEDs
+ Check passive values for rationalisation; e.g. standardise on 100nf
if possible etc. same for resistors.
(As yet incomplete)
+ Any need of track impedance for delicate signals. Not required, short
+ Power Planes and return tracks for delicate signals. No power planes,
2 layer board. No differential signals, all returns to ground plane.
+ all components mounted on the UNDERSIDE of the PCB
-- rest of layout
Here are links to the data sheets for the main components:
Summary of bugs and changes:
Voltage reference IC U4 changes to NCP51460SN33T1G - a 3.3V SOT23
voltage reference, RS part 719-2642
Nand gate IC1 changes to AND gate SN74AHC1G08D8VR, RS part 526-436
R21 changes to 200k, new value of resistor.
R22 changes to 10k, an existing value
R23 changes to NM (not mounted)
The LED changes to L-710A8GE/2LGD-RV (2 green LED's, as the Red/Green
had the wrong Cathode), RS part 616-4116
A flying lead is required from the MAX1932 Pin 12 (CS bar) to Pin 42 of
the Arduino shield to enable the signals for the power supply set point.
In general a fairly good bill of health for the design. Communications
(address ack.) has been checked for both I2C busses, verification of the
I2C device functionality is still on the list of things to do.
Comments as we went along:
Wrong part for the indicator LED (anode and cathode are swapped) - to be
Very hard to get the Arduino off once it's pushed in.
The 4.096V reference is too high. Needs to be changed to something 3.3V
or lower. Precision is currently approx 200mV steps on the trigger
The !CS isn't connected to the arduino - needs pinning out to Digital
Observed Vout from Vbias is 39V; limit value from the Zener. Killed the
HV PSU on board 1!
NAND Gate to be swapped for AND Gate.