FMC ADC 100M 14b 4cha - Gateware Release 2.0 for SPEC
Bitstream
A binary bitstream file is available in the Documents section.
Memory map
Documentation
Please refer to the release 1.1 gateware manual
Sources
The sources are in the Git repository and tagged with "spec-fmc-adc-v2.0".
Release date
- 29 July 2013
Release notes
- Fix bug in pre/post_trig_done signals generation.
- Update wbgen wishbone interfaces (port name change).
- Change utc core name into timetag core.
- Takes the adc data for trigger threshold after offset/gain correction block.
- Move mezzanine related wb cores to a separate module.
- Rename top level fmc slot ports to be compatible with the svec (2 fmc slots).
- Change spec mapping to fit the svec mapping.
- Change serdes pll feedback.
- Add a software reset register to reset the mezzanine related cores.
- [ddr core] Fix wishbone interface to ignore stb if cyc is '0'.
Matthieu Cattin - July 2013