PCB Layout review of FMCADC100M14b4cha version 1 (EDA-02063-V1)
24 March 2010
PCB layout of 2010-03-12
Maciej Fimiarz (designer, BE/CO), Pablo Alvarez (BE/CO), Matthieu Cattin
(BE/CO), Erik van der Bij (BE/CO), Tomasz Wlostowski (BE/CO).
General description of the PCB layout.
The detailed PCB layout has been made by the design office of the
EN-ICE-DEM with input from Maciej. It is a 6-layer board. There are two
solid ground planes, while the eight different supply voltages are
carried by wide tracks. The four channels are somewhat spaced apart, no
other measures are believed necessary for channel separation.
Detailed comments on the PCB layout
The following sections give a global idea of the improvements proposed
during the review. It is not an exhaustive list.
Make supply lines wider (plane like), possibly by making other
signal lines smaller. Despite the fact that the currents are low,
this will provide a small distributed decoupling capacitor (10's of
Put more vias under the LDO in the top-right corner for better heat
Reroute clock input from the FMC connector. This allows removing of
vias in the main clock line.
Swap the local clock oscillator outputs. This allows removing vias
in the local clock line.
Move filter on P12V from the lower part of the card to the top. This
was the long line carries a clean signal.
In the area of R29/R30/C13 cleanup so a via on P1V8 can be removed
and power tracks can be widened (notably M8V).
Rotate L9 so can remove via in plane.
Space vias further apart (or make clearing smaller, to be checked
with DEM) to remove large splits in ground planes and power tracks.
Vias of the FMC connector should be covered with solder mask.
Large metal pad under ADC: split into four smaller areas to have
LD1 silkscreen over a pad (possibly on wrong layer in PCB -
Make all vias bigger.
Move texts on silkscreen to be not on top of vias.
Add several texts with full name of card (FMCADC100M14b4ch) and also
in full text: e.g. "100 MSPS, 14-bit, 4 channel ADC".
FMC connector: mark rows (A, B, C, ...) and pins 1, 10, 20, 30, 40.
To be verified
Verify if each IC and plane has correct decoupling capacitors.
This has been a very useful review that introduced several improvements.
Overall the layout was already fine and would have given a working
board. Certain of the suggested changes will make the layout better,
likely improving SNR and EMC features. Other changes will improve the
production process or are just cosmetical.
To gain time, it has been decided that Maciej and Tomasz will do the
changes before submitting them to the design office again.
We thank all people involved in the review.