FMC DAC 250MSPS 16b 4CH
Project description
The FMC DAC 250MSPS 16b 4CH is a single width mezzanine card (69 x 76.5mm) that has been specifically designed to be plugged on the VXS DSP FMC Carrier card but other carriers may also be used. The mezzanine card is using a High Pin Count (HPC) connector that provides up to 400 pins, from which 160, are used definable. The stack height of the connector is 8.5mm. Therefore, the mezzanine card also needs a carrier with a HPC connector and the clock signal for the mezzanine should be provided by the carrier. The mezzanine card is designed according to a VITA57.1 FPGA Mezzanine Card (FMC) standard that sets the specifications for the electromechanical aspects of the mezzanine card. For more information, see FMC standard.
The FMC DAC 250MSPS 16b 4CH card receives digital data input from an FPGA. This data is sampled with four digital-to-analog converters that provide four identical analog outputs. These outputs are amplified, filtered with a 40MHz cutoff frequency and four RF-signal outputs of max. 3.8Vpp are provided by the mezzanine card. The 3.8Vpp voltage is the saturation point of the driving amplifier. In addition, the board has a Serial Peripheral Interface (SPI) for D/A-converter and A/D-converter control; an Inter-Integrated Circuit (I2C) bus that connects devices such as a voltage/temperature monitoring chip, a 64-bit identification number chip, I2C-to-1-wire bridge, an EEPROM memory and a front panel LED controller chip.
Hardware images
Top layer of the mezzanine card (version
2)
Bottom layer of the mezzanine card (version 2)
- Front panel of the mezzanine card (same with all versions)
Block diagram
Main features
-
Output
- 4 identical channels
- each 50 ohm series terminated with SMC connectors in the output, 8.5mm front panel covering the output
-
Bit resolution
- 16 bit
-
Peak maximum output Upp
- +/- 3.8V (amplifier saturation point) or 80mA (amplifier max. output current), DC-coupled 50ohm line
-
Output scaling factor, Upp/8
- 18dB attenuator DC-coupled, output selected with a switch (between 0dB and -18dB)
-
Analog Bandwidth
- 40 MHz
-
DAC sampling frequency
- 250 MSPS
- AD9747 Dual DAC pipeline delay 7-8 clocks
-
Clock source
- 2 differential external clock lines are distributed via FMC connector
-
Signaling standards
- LVCMOS33 for input data, LVTTL33 for some of the I/O control signals and LVPECL/LVDS for the differential input clock signals
-
Interface between mezzanine and carrier
- VITA 57 FMC High Pin Count 400-pin connector, FMC connector stack height 8.5mm
-
Standard for the daughter card
- FMC standard (VITA 57) that specifies the electrical and mechanical aspects
Project information
- Official production information at CERN EDMS (Equipment Data Management Service) EDA-02069
- The design is currently used only for CERN RF-group purposes
Hardware versions
Version 1 (obsolete)
- Version 1 hardware images (top and bottom layers)
-
Transition board - EDA-02227
used for test purposes.
- An error with the decoupling in the last page of the schematic, page will be updated for the V2
Version 2 (working prototype version)
-
Transition board - EDA-02227
used for test purposes.
- An error with the decoupling in the last page of the schematic, page will be updated for the V2
Contacts
General questions about the project
-
Petri Leinonen -
CERN-BE-RF-FB
- The hardware designer and the manager of the project leaves CERN
in the end of May 2013
-> contact persons starting from the 1st of June 2013 are Jorge Sanchez Quesada and Alfred Blas
- The hardware designer and the manager of the project leaves CERN
in the end of May 2013
Status
Date | Event |
---|---|
Jun 2009 | Project hardware planning starts |
Jul-Dec 2009 | Planning specifications; selection of FPGA Mezzanine Card (FMC) standard for the project and adapting to the modifications; changing the FPGA family from Altera to Xilinx and placing the FPGA on the carrier according to the FMC standard; etc. |
15-01-2010 | Start of the mezzanine hardware design |
20-05-2010 | Ordered the components for the V1 HW prototypes |
08-09-2010 | Last components arrive. Multiple shipment delays occured with the distributors during the summer months. |
08-09-2010 | Mezzanine hardware schematic and simulation finished |
15-09-2010 | Transition board schematic started. This module was designed to interface between the mezzanine and ML605 evaluation kit for testing purposes. The transition board manages signal level translation and clock generation between the two boards |
15-09-2010 | Start of the PCB layout work |
18-10-2010 | Layout work finished and PCB manufacturing started |
04-11-2010 | PCB fabrication finished and assembly started |
16-11-2010 | Mezzanine card manufacturing finished, 6 PCBs produced and 3 of them were assembled |
13-12-2010 | Transition board schematic and simulations finished |
13-12-2010 | Transition board layout started |
12-01-2011 | Transition board components ordered |
07-03-2011 | Transition board manufacturing finished |
15-03-2011 | Transition board tests finished. See official information EDA-02227 |
01-04-2011 | Firmware development started |
06-06-2011 | V1 of the firmware for testing purposes finished |
15-12-2011 | V1 Hardware tests finished together with final test FW, see Test-results-V1 |
16-12-2011 | V2 Hardware design started |
08-02-2012 | V2 Hardware design finished, CERN design office started working with the V2 |
15-03-2012 | Series production, 37 boards, components ordered |
16-03-2012 | Layout work of V2 finished, Hardware changes to V1 |
02-04-2012 | Production of 12 PCBs of V2 finished |
24-04-2012 | Initial version of the memory map version created with a new software Cheburashka and the register control with Gena ((links only visible from inside CERN) |
25-04-2012 | Initial version of the register control created and tested with the HW V1 |
27-04-2012 | Memory map structure finalized |
07-05-2012 | Components brought to the manufacturing workshop at CERN. All components have not yet arrived |
14-05-2012 | Memory map updated and tested with HW V1 |
21-05-2012 | All components arrived. Assembly started |
29-05-2012 | V2 HW assembly finished, 12 PCBs manufactured and 10 of them were assembled |
20-06-2012 | Smoke test V2 HW ok. All power supplies within tolerance, see Test-results-V2 |
06-08-2012 | Testing of the V2 HW prototypes (10 pcs) will be started on the 9th 14th of August 2012, see Issue #572 |
09-08-2012 | Took 9 of the V2 boards to the CERN design office for modifications, see Issue #9 (closed), #8 (closed) and #7 (closed) for the modification information |
16-02-2013 | Installed the V2 Hardware to the PS Booster control room and officially finished the V2 HW and FW tests. |
12-04-2013 | V3 hardware launched at CERN. Hardware changes to V2 |
28-05-2013 | The hardware designer and the manager of the project leaves CERN in the end of May 2013, contact persons starting from the 1st of June 2013 are Jorge Sanchez Quesada and Alfred Blas |
Petri Leinonen - 28th of May 2013