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FMC V1
This document contains the schematics of the FMC V1.
They are two executions:
1) V1-0 without hysteresis:
https://edms.cern.ch/ui/\#\!master/navigator/item?P:1993661833:1625242383:subDocs
2) V1-1 with hysteresis:
https://edms.cern.ch/ui/\#\!master/navigator/item?P:1993661833:1493993345:subDocs
Schematics, second draft
Having gathered all hints and remarks about the first draft of the FMC DIO 10I8O allowed a second draft to be produced.
The FMC DIO 10I8O has 10 inputs on which it will be possible to set two
bipolar references (between +-5V) using 2 comparators (LMH7324 model)
per input.
The comparator hysteresis has been increased using a feedback.
The references are set using DAC (7716 model), communicated through SPI-daisy chain.
Files provided:
- Schematics
- Bill of materials
- Hysteresis calculations
- Current required
- Netlist
Schematics, first draft
The FMC DIO 10I8O has 10 inputs on which it will be possible to set two bipolar references using 2 comparators (LMH7324 model) per input. The hysteresis has been added with a feedback.
The references are set using DAC (7716 model), communicated through
SPI-daisy chain.
Termination input is selectable through I2C from the FMC.
There are 8 monitored outputs using an octal line driver (sn74bct25244).
Communication from the comparators outputs and the FPGA uses LVDS.
LVDS signals are also used to activate the line driver outputs through a
LVDS receiver.
Input voltages: +-5V.
I/O on FMC connector side: compatible with 1.8 and 2.5V
This board is designed primarily to deal with the pick-up and trigger signals that can be found in the TE-ABT-EC environment, which is dedicated to the controls of the kicker magnets.
All comments are more than welcome.