Specification
- Single width FMC mezzanine
(ANSI/VITA.57,
Chapter 3.2)
IMPORTANT: The FieldTR transformer is ~1 mm higher than what the standard permits. Due to that, the carrier board should have a cut out under the FMC board (see e.g. the SPEC board). While it is possible to mount FMC-nanoFIP on a carrier without the cutout, it may create undesired mechanical stress (see mounting FMC-nanoFIP on SVEC carrier).
IMPORTANT: The FMC standard says a mezzanine should provide an EEPROM, but due to radiation tolerance requirements it is not desirable. There is a footprint to mount an EEPROM, but the component is not mounted by default. If there is a justified request, EEPROM can be emulated using the nanoFIP FPGA.
* WorldFIP interface implemented using nanoFIP:
- standard DB9 male connector with 4-40 UNC threaded bolt for cable
locking
- 2x1 2.54 mm pin header for board-to-board connection
* FMC interface:
- FMC low pin count connector (ANSI/VITA.57, Table 3).
- Requires 12V & 3.3V as in the VITA.57 standard.
- LVTTL I/O levels.
- Unused pins in the nanoFIP FPGA will be routed to the FMC connector.
- Variable data transfer over an integrated memory accessible with an 8-bit-data, 10-bit-addr WISHBONE interconnection.
- Stand-alone mode with 8 input and 8 output lines without the need to transfer data to or from memory.
- Separate data valid outputs for each variable (consumed and
produced).
- JTAG to reprogram a companion FPGA (on the carrier board) using the
nanoFIP link.
TODO pinout*
* Reset (more):
- External pin available on the FMC connector (might be disconnected by removing a 0 ohm resistor)
- Addressed reset by broadcast consumed variable validated by station address as data
- Power-on reset
- Reset output available to external logic via the FMC connector
* Estimated power consumption (based on nanoFIP test report):
- 90 mA / 3.3V (FPGA 3.3V and 1.5V LDO; LEDs)
- 75 mA / 12V (5V LDO at 70% efficiency for FielDrive and FieldTR which
consume ~120 mA / 5V in total)
- 2 LEDs indicating FIP link and Wishbone bus activity.
- JTAG connector (standard 2x5 2.54 mm pin header) Actel FlashPro 4 pinout) for the nanoFIP FPGA and a jumper to disable reprogramming.
- Radiation tolerance up to 200 Gy.
- 8 low-profile dip switches on a top to configure the station address (accessible without removing the mezzanine from the carrier board).
- Constructor and model IDs set by dip switches.
Design constraints
* Board:
- Single width FMC form factor
- Cut out zone in the carrier board limits the area where the FieldTR transformer can be placed (see e.g. the SPEC board)
- FIP 2x1 pin header has to be placed away from the cut out zone (it
should be possible to connect it to a carrier board with a female pin
header)
- DIP switches have to be placed on top, so they are accessible without
removing the board from the carrier
- Front panel:
- DB9 connector is almost of the same height as the front panel bezel. It has been verified with 3D models that the selected DB9 connector will fit.
Other designs
There is a number of designs that may serve as a reference for schematics:
- FMC MasterFIP: https://edms.cern.ch/ui/\#\!master/navigator/item?P:1187203503:1037329200:subDocs
- FGClite: https://edms.cern.ch/ui/\#\!master/navigator/item?P:1169840490:1067623240:subDocs
- nanoFIP Test Board: https://www.ohwr.org/project/nanofip-test-board
- nanoFIPdiag: https://www.ohwr.org/project/nanofipdiag
- Alstom board: http://cern-worldfip.web.cern.ch/cern-worldfip/Docs/Hardware%20Modules/Alstom%20Cards/CC130-131-132%20User%20Reference%20Manual-ENG.pdf
30 Apr 2018