Switch Planning for 2010
This is a quick description of the work packages for getting a first version of the WR switch by the end of 2010, with basic switching capabilities and good timing. The following explanations and task numbers refer to the attached Gantt chart: attachment:wrswitch2010.pdf. Explanations are only given when the title of a work package is deemed not sufficient for understanding.
1. General Specs.
Informal WR spec.
1.1.This is a not-very-long document telling developers what WR is and how one goes about designing a node. In particular, it describes the enhanced PTP mechanism. The real WR spec is delivered in 6.1. after a whole year of learning.
1.2. Basic switch spec.
Here we decide which features of the relevant IEEE standards apply to this first version of the switch, how many ports, and other miscellaneous features such as basic switch management through SNMP.
1.3. Switch use cases.
1.4. V3 switch PCB specs.
2. V3 Switch PCB.
2.1. Design.
2.2. Manufacturing.
2.3. Testing.
3. Switch HDL.
HDL for both FPGAs in the v2 MCH design.
3.1. Timing HDL design.
Enhanced PTP, DMTD phase shifting, etc.
3.2. Switching function HDL design.
NIC, End Point, switch fabric, etc.
4. Switch FW
4.1. Kernel code
- Board's main infrastructure. kernel to user-space interface to load firmware and configure the board
- Driver for the switch with HW timestamps' support
- Try to get this merged into the mainline kernel
4.2. User-space code
- PTP daemon
- SNMP
- RSTP
5. Testing.
5.1. Networking tests.
Checking compliance with the IEEE features specified in 1.2. Also stress tests.
5.2. Timing tests.
Precision, jitter and phase noise tests.