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Wishbone slave generator

wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:

- Automatically allocated memory layout

- VHDL/Verilog code for the slave module

- C header files for driver development - Nice HTML documentation

Read the wbgen2-Documentation Get the latest version binaries https://www.ohwr.org/attachments/5659/wbgen2-bin.tar.bz2

Project ID: 10695
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