White Rabbit integration into IEEE1588-2019 as High Accuracy
This page summarizes how White Rabbit (WR) found its place in IEEE1588-2019 Precision Time Protocol (PTP) as High Accuracy (HA) profile and optional features. The page gives a general overview regarding the split of WR into parts and how these parts where translated into standard's language. The clause/annex numbers are with respect to the published version of IEEE1588-2019.
You can start with The New High Accuracy Default PTP Profile in the IEEE 1588 Draft Revision presentation for a quick overview. Note that this presentation is based on a draft version of the standard in which annex numbers were different than in the final published versions.
Overview
The following parts of WR were distinguished:
- Control of L1 syntonization by PTP
- Estimation of delay asymmetry and correction of PTP calculations for delay asymmetry and hardware delays
- Calibration of hardware delays and relative delay coefficient (needed to estimate the delay asymmetry)
- Assignment of fixed master/slave roles to ports
- Dedicated WR Profile compatible with Delay Request-Response Default PTP Profile
These parts were generalized (to make them useful on their own) and integrated into the IEEE1588 standard. The integration takes few forms:
- Optional features - included in clause 16, 17 and Annex L - some of these features are HA-specific, other much more generic
- New Default PTP Profile - Annex I.5
- Informative annex - Annex N
Additionally, a number of changes were made to the core parts of the standard to allow the optional features. There is also an informative Annex M that describes sub-ns implementation of the new "High Accuracy Delay Request-Response Default PTP Profile" - this is effectively a description of the new High Accuracy incarnation of White Rabbit.
The figure below gives a general overview of how WR has been integrated into IEEE1588. The next section of this page translates the WR parts into IEEE1588 clauses/annexes. The last section of this page lists all the annexes/sections in the new IEEE1588-2019 that are relevant for HA/WR and explains their relevance.
Translation of WR parts into IEEE1588-2019 annexes/clause
-
Control of L1 syntonization by PTP which means that the
master-slave hierarchy used by PTP to distribute time from
Grandmaster is also used to distribute frequency using L1
syntonization:
- Annex L: Layer-1 based syntonization performance enhancements (L1Sync) - this annex is more generic and provides more capabilities than needed by WR
-
Estimation of delay asymmetry and correction of PTP calculations
for delay asymmetry and hardware delays:
- Clause 16.7: Configurable correction of timestamps (optional)
- Clause 16.8: Calculation of the delayAsymmetry for certain media (optional)
-
Calibration of hardware delays and relative delay coefficient
(needed to compensate delay asymmetry):
- Annex N: Calibration Procedures
-
Assignment of fixed master/slave roles to ports - two different
optional features to control PTP Port state:
- Clause 9.2.2.2 and 8.2.15.5.2: MasterOnly mode of PTP Ports
- Clause 17.6: Mechanism for external configuration of a PTP Instance’s PTP Port state (optional)
-
Dedicated WR Profile compatible with Delay Request-Response
Default PTP Profile:
- Annex I.5: High Accuracy Delay Request-Response Default PTP Profile
-
Explanation of how to implement sub-nanosecond synchronization using the High Accuracy Profile
- Annex M: Sub-nanosecond synchronization using the High Accuracy Default PTP Profile
Annexes/Clauses in IEEE1588-2019 relevant for HA/WR:
3. Definitions, acronyms and abbreviations:
- New definitions have been added and old definitions extended to facilitate specification of HA-related text
- HA-relevant definitions: clock, clock signal, Direct PTP Link, implemented message timestamp point, layer-1 transmit (L1 tx) clock signal, layer-1 receive (L1 rx) clock signal, Local Clock, Local Clock signal, Local PTP Clock, Local PTP Clock signal, synchronized clocks, syntonized clocks, time counter
5.3.11 RelativeDifference:
- New data type to store alpha parameter (scaledDelayCoefficient) in configurable member of a new data set (asymmetryCorrectionPortDS). This allows makinthe alpha parameter a configurable value.
7.3.4.2 Timestamp generation:
- Divided correction of timestamps into two parts:
- Implementation-specific part applied "outside PTP" and provided by the hardware - bitslide in WR
- Corrected by PTP, provided via configuration (i.e. data set members: ingressLatency and egressLatency) - fixed deltas in WR
- This clause has been redone (compared to IEEE1588-2008) to allow implementation-specific correction of ingress/egressLatencies (WR's bitslide) before PTP corrects for the ingressLatency and egressLatency - this values are equivalent to fixedDelays and are used instead in HA
7.4.2 PTP Communication Path delay, PTP Link delay, and delayAsymmetry:
- This clause has been redone (compared to IEEE1588-2008) to allow estimation of delay asymmetry using HA-specific optional feature in 16.8
- Two types of meanDelay (meanPathDelay and meanLinkDelay) are defined now to increase readability of the standard, including calibration procedures in Annex Q
7.4.3 Medium relative delay coefficient:
- Added to define medium relative delay coefficient (scaledDelayCoefficient) which is the alpha in WR
7.6.2.6 clockAccuracy:
- Extended range to picoseconds
8.2.15.5.2 portDS.masterOnly:
- Member of portDS that stores configuration of masterOnly optional feature
8.2.16 timestampCorrectionPortDS
- New data set that stores hardware delay corrections, called ingressLatency and egressLatency in IEEE1588 (called fixed delays in WR).
- Unlike in WR where fixed delays of the master and slave ports are corrected only by the slave port, in IEEE1588-2019 the master port corrects its timestamps and the slave port corrects its timestamps for ingressLatency and egressLatency
8.2.17 asymmetryCorrectionPortDS
- Data set with members that are used by the optional feature in 16.8: "Calculation of the delayAsymmetry for certain media (optional)" - this feature allows dynamic calcuation of portDS.delayAsymmetry. This value is then used to correct meanDelay.
- The members of this data set include:
- scaledDelayCoefficient (alpha in WR) parameter - defines relative difference between master-to-slave and slave-to-master delays
- enable (not present in WR) - it enables/disables dynamic calculation of delayAsymmetry,
- constantAsymmetry (not present in WR) - it is a static offset that
can be used to:
- fine-tune the delay asymmetry calculated using delayCoefficient (alpha),
- account for active elements,
- manually configure delay asymmetry when scaledDelayCoefficient is not know (scaledDelayCoefficient is set to zero in this case).
8.2.23 L1SyncBasicPortDS and 8.2.24 L1SynsOptParamsPortDS
- Data sets used by the optional feature defined in Annex L: Layer-1 based syntonization performance enhancements (L1Sync)
8.2.28 externalPortConfigurationPortDS
- Data set used by the optional feature defined in 17.6: Mechanism for external configuration of a PTP Instance’s PTP Port state (optional)
- Its data set member "desiredState" stores the desired state of the PTP state machine
9.2.2.2 MasterOnly PTP Ports
- This is a generic (i.e. non-HA-specific) feature that can be useful in HA devices (it is not enabled by default), it can be used to enforce timing topology, similarly to current WR
- Tt prevents a PTP port from entering PTP Slave state by ignoring received Announce messages (thus, the BMCA will see no foreign masters and it will always decide that the PTP Port should be a Master)
12.2.3 Syntonization based on other mechanisms
- The original clause modified to make it HA-friendly
- HA explicitly mentioned
16.7 Configurable correction of timestamps (optional)
- It defines a feature that mandates correction of timestamps for ingressLatency and egressLatency (i.e. fixed delays in WR)
- The value of timestamp corrections are configured through the members of the new timestampCorrectionPortDS
16.8 Calculation of the delayAsymmetry for certain media (optional)
- It defines a feature that calculates the delayAsymmetry using scaledDelayCoefficient (alpha in WR) and uses the calculated value to
- update the portDS.delayAsymmetry data set member
- correct meanDelay in the calculations of offsetFromMaster (synchronize)
- The value of scaledDelayCoefficient (alpha) is configured through the member of the new asymmetryCorrectionPortDS
17.6 Mechanism for external configuration of a PTP Instance’s PTP Port state (optional)
- This is a generic (i.e. non-HA-specific) optional feature that can be useful in HA devices (it is not enabled by default)
- It allows to manually configure PTP states
- It can be used to enforce timing topology, similarly to current WR
I.5 High Accuracy Delay Request-Response Default PTP Profile
- A new Default PTP Profile
- It mandates:
- implementation of HA optional features and generic features useful for HA, it specifies their parameters
- enabling HA optional features
- It specifies the High Accuracy model of Local PTP Clock (I.5.5)
- It is inter-operable with the Delay Request-Response Default PTP Profile, and Peer-to-Peer Default PTP Profile if the peer-to-peer mechanism is implemented
- If it is properly implemented, this is effectively White Rabbit
Annex L: Layer-1 based synchronization performance enhancement
- It allows and formalizes cooperation between L1 syntonization and PTP synchronization in terms of distribution hierarchy
- It provides terms for relations between L1 syntonization and PTP: transmit coherent, receive coherent, congruent
- It allows PTP to get/set the relationship between L1 syntonization and PTP (tx/rx coherency, congruency)
- It allows to recognize HA devices and their capabilities, in this way interoperation of the HA Default PTP Profile with Delay Request-Response Default PTP Profile is achieved (Peer-to-Peer Default PTP Profile, if peer-to-peer mechanism is implemented)
- It has an optional part that is potentially useful in applications of PTP along with SyncE, in particular in applications in which distribution hierarchies of PTP and SyncE are not congruent/aligned.
Annex M: Sub-ns synchronization using the High Accuracy Default PTP Profile
- It describes how to implement the HA Default PTP Profile and the HA optional features such that sub-ns accuracy is achieved
Annex N: Calibration Procedures
- It is a translation of WR Calibration into a more generic standard language
Last update: 13-06-2020 by Maciej Lipinski