The external clock input provided by the WRS Low Jitter daughterboard is
processed by a DDMTD block. The DDMTD can be sensibile to the internal
clocks inside the FPGA. To avoid any noise coupling the gateware has
been built using a PBLOCK constrain to exclude any logic around
clk_i_d0 and clk_i_d1 of the ddmtd_with_deglitcher.vhd DFFs (the
ones that are used to demodulate the input clock). Additionally, these
DFFs are manually placed.
Unfortunately the PBLOCK constrain is sometimes ignored by MAP due to a
bug. A correct image of the FPGA must be check with FPGA editor (looking
for ext_clk_62* lines). A correct image is as follows:
The published gateware has been validated by manually moving the phase
set-point at 100ps steps to check if any jumps were detected while
running in GM mode (using 3120A). None of them were detected.
A working GM should have a Modified ADEV at 1s of less than 5E-13. If a
value greater than that if measured, check with 3120A if some jumps were
If you see some jumps like these ones then you ahave a noise
Check with FPGA editor if any external logic has been placed around the
This kind of noise is probably due to ground bouncing. Since the nearby
DFFs are switching using clk_sys, which is phase related to the clock
provided by the WRS Low Jitter, if you're unlucky the external clock
edge is near the clk_sys edge, providing this kind of jumps. Check on
the FPGA Debug console Setpoint value if the Setpoint value, Setpoint
mod 8192 is below 2000 or above 6000. If yes, reboot the switch and
retry to measure it when it's around 4000.
The provided gateware doesn't show this kind of effect, however an easy
workaround (in case you keep to experience this kind of noise with a
rebuilded gateware) is to keep resetting the PLL of the WRS Low jitter
board until the external clock is not near the clk_sys clock edge. This
is very feasible modifying spll_external.c FSM. This has not been
implemented since on the provided gateware the jump effect was not
visible on any 100ps steps.