When running with a 40MHz clock it is not possible to generate subsequent bunches. But generating every second works OK.
Not a bug but a limitation of the implementation.
When running with a 40MHz clock it is not possible to generate subsequent bunches. But generating every second works OK.
There seems to be no way to add set_parameter
assignments in the Quartus project.
Note the syn_properties
attribute maps to set_global_assignment
.
Can you please expose the generic g_interface_mode
of xwrc_board_common
on the top level of xwrc_board_vfchd
?
Tom Levens (f50d79fc) at 25 May 12:32
Add g_ASYNC_DTACK to verilog wrapper
Closes #28
Tom Levens (a0ca042e) at 25 May 12:23
Tom Levens (41ef3252) at 13 Mar 08:03
FWIW, I have resolved the merge conflicts and pushed the result to a new branch develop-merge-master. The changes are here:
develop...develop-merge-master
It is not possible to update the source of this MR, but this branch can be merged into develop without conflicts. Maybe nicer to do this as a fast-forward to avoid a double merge commit?
git merge --ff develop-merge-master
Here is the minimised version of the XCIX: adc_memory_min.zip