Hdlmake includes the target file when generating a simulation Makefile
On 03/11/2016 03:14 PM, Maciej Sumiński wrote:
> I might have found a minor bug in hdlmake: it includes the target
file
> when generating a list of dependencies when a simulation Makefile
is
> prepared. Example:
>
> file1.vhd: file1.vhd file2.vhd file3.vhd
> vcom $(VCOM_FLAGS) -work work $<
> mkdir -p $(dir $
) && touch $@
>
> Notice that file1.vhd is on both sides of the first line and make
does
> not like that.
>
> The patch introduces a similar condition as in the Verilog case, so
I
> believe it should be fine here as well.