String Element inside $display Verilog function will be misinterpreted as module
Inside verilog module, inside a $display function; the first string element will be misinterpreted as (unresolved) Module:
WARNING new_dep_solver.py:91: solve() Relation Use module 'work.nomodule' in ps2mouse.v not satisfied by any source file
module ps2module ();
task configure;
begin
$display("NoModule dontmatter (0xff)");
end
endtask
endmodule