Custom CSR registers make use of reserved area
The following additional CSR registers of the VME64x core (not part of the standard) are implemented in an area reserved by the ANSI/VITA 1.1-1997 for future use.
IRQ_Vector | 0x07FF5F |
IRQ_level | 0x07FF5B |
MBLT_Endian | 0x07FF53 |
TIME0 | 0X07FF4F |
TIME1 | 0X07FF4b |
TIME2 | 0x07FF47 |
TIME3 | 0x07FF43 |
TIME4 | 0x07FF3F |
BYTES0 | 0x07FF3b |
BYTES1 | 0x07FF37 |
WB32bits | 0x07FF33 |
These are documented in Section 2.1 of the VME64x user manual (Table 1).
According to the standard, Table 10-13, the region [0x7FC00..0x7FF5F] within the "Defined CSR Area" is reserved and should always read zero (rules 10.13 and 10.14 in section 10.2.2).
Instead the standard provides the "User CSR Area" for design-specific registers (section 10.2.5), which the VME64x core should use for the registers listed above.