V1 - GTP clock inverted
The reference clock for GTP 245 (part IC19L) is inverted on FPGA_GTP.SchDoc (FPGA_PLL_REF_CLK0_N port connected via C162 to MGTREFCLK0P and vice versa).
The reference clock for GTP 245 (part IC19L) is inverted on FPGA_GTP.SchDoc (FPGA_PLL_REF_CLK0_N port connected via C162 to MGTREFCLK0P and vice versa).