Bug #740

V5-0 - P8V power supply startup problems

Added by Tomasz Wlostowski on 19 Apr 2013 at 00:23. Updated on 13 Jun 2013 at 14:47.

Status:Closed Start date:2013-04-19
Priority:Immediate Due date:
Assignee:Tomasz Wlostowski % Done:

0%

Category:- Spent time: -
Target version:-

Description

The switched mode PSU (LT3503) on some cards (V5+) has problems with starting up: it never exits current limit mode, because of high load capacitance of the decoupling capacitors (10 x POSCAP 47 uF) combined with their very low ESR.

As a result, we get very noisy P8V rail, which disturbs the ACAM delay line PLL linear power supply, increasing the jitter of measured timestamps 3-4 times. The bug was unnoticeable to the PTS because it currently measures only average delay.

Actions:
1. Replace all 47 uF POSCAPs with 10 uF POSCAPs (10 pcs / board)
2. Update the PTS to characterize TDC jitter of each card.

History

Updated by Erik van der Bij on 26 Apr 2013 at 14:50

  • Status changed from New to Assigned

Also create new production files (V5-1)

Updated by Erik van der Bij on 15 May 2013 at 15:21

  • Subject changed from P8V power supply startup problems to V5-0 - P8V power supply startup problems
  • All boards delivered to CERN were repaired
  • Documentation updated with new capacitor values in V5-1 EDMS release.

Updated by Erik van der Bij on 13 Jun 2013 at 14:47

  • Status changed from Assigned to Closed

Tom and I checked EDMS: OK.
Repaired cards need still calibration. Will be done by Tom.

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