SPI flash PROM latency
the SPI i/f between FPGA and flash eeprom contains latency that needs to be taken into account if clock rate is substantial.
M25P32 from Micron specifies max latency:
8 ns from falling edge of clk to valid output data.
SN74LVC1G97 multiplexer fron TI specifies max latency:
6.3 ns from input to output.
clock rate on picture under is 40 MHz. from FPGA's point of view, data
is latched out on rising edge of the
clock.