Description
The AsyncArt Project is comprised by a set of Open-Source HDL libraries and examples targeted to the efficient implementation of Globally Asynchronous, Locally Synchronous (GALS) design architectures over Commercial-Off-The-Shelf FPGA devices.
Application
A GALS circuit consists of a set of locally synchronous modules communicating with each other via asynchronous wrappers. In this way, each synchronous subsystem ("clock domain") can run on its own locally generated independent clock (frequency), while sharing data with their neighboring modules by using asynchronous micropipelines.
One of the critical advantages of GALS over pure synchronous designs is the much lower electromagnetic interference (EMI). The CMOS circuit (logic gates) requires relatively large supply current when changing state from 0 to 1. These changes are aggregated for synchronous circuit as most changes are initialized by an active clock edge. Therefore, large spikes on supply current occur at active clock edges in synchronous designs. These spikes can cause large electromagnetic conducted and radiated interference, and may ultimately lead to circuit malfunction. In order to limit these spikes large number of decoupling capacitors are used, but this is not always possible and no more than hack for the actual problem.
Another solution is to use a GALS design style: there are different (e.g. phase shifted, rising and falling active edge) clock signal regimes thus supply current spikes do not aggregate at the same time. Consequently, GALS design style is often used in System-on-Chip (SoC) devices, being of special interest for Network-on-Chip (NoC) based architectures.
Technical Details
More than a standard library, the core of the AsyncArt project is a collection of very simple reference design examples that contain useful tricks and methodologies that can be easily extended to more complex projects.
The original AsyncArt research project was conducted by Javier Garcia-Lasheras between 2005 and 2007 with the support of the Communication, Signal and Microwaves group of the Public University of Navarre. The target for this research was to demonstrate the advantages of a full featured System-on-Chip ASIC implemented with the GALS approach. After heavy testing in FPGAs, an ASIC chip dubbed PNX-2006 was successfully built, demonstrating Asynchronous Network-on-Chip capabilities and active power consumption and EM interference reduction techniques.
During the research, we noticed that the FPGA prototypes performed very close to the physical limit of the technology while incurring in a very low logic overhead. Being aware of this being a major breakthrough, we published the internal details for our GALS implementation for FPGAs in the following paper:
Original reference designs
Five years later, in 2012, the experimental FPGA projects that served as prototypes for the PNX-2006 ASIC chip were published as free/open source in the Open Hardware Repository. Those designs were implemented over Xilinx devices and are distributed as a collection of schematic projects for Xilinx ISE. You can find the collection with the original example projects in this link:
AsyncArt blog series
An AsyncArt Quick-Start was originally published as a blog series on All Programmable Planet, an online community sponsored by Xilinx. After this community was closed, the blog series was republished in the EETimes:
-
Asynchronous Design: Grabbing You by the
GALS
- One of the most promising solutions to the issue of connecting multiple IP cores on a single silicon chip is the Globally Asynchronous, Locally Synchronous approach, a.k.a. GALS.
-
Entering the
Micropipeline
- We review the main underlying concepts of micropipelines before deploying them in real FPGAs.
-
The AsyncArt Project: Asynchronous Open Hardware for
FPGAs
- Here we see a suite of circuits that demonstrate different aspects of asynchronous micropipelines.
Licensing
The licensing policy of the AsyncArt project is quite simple and can be resumed in the nexts facts:
- You are granted to use the HDL code provided as a IP-Core library in any design, and by doing this you are not forced to disclose the other IP-Cores involved in the system.
- If you change or improve the HDL code in any way, you must share your modifications with the open-source design community.
To clarify the licensing terms, we have chosen the LGPLv2.0 license, the most optimal available one, in order to fullfill the previous facts in a satisfactory way.