Project description
This core is a DDR3 controller with two pipelined Wishbone slave
ports.
It is based on the Spartan6 hardware core and a management core
generated by Xilinx
CoreGen.
Overview
Documents
ug388 - Spartan-6 FPGA Memory Controller User
Guide
ug416 - Spartan-6 FPGA Memory Interface Solutions User
Guide
check Xilinx website for latest version:
http://www.xilinx.com/support/documentation/ipmeminterfacestorelement_meminterfacecontrol_mig.htm
Date | Event |
16-08-2010 | Xilinx memory controller study |
18-08-2010 | Write a wrapper around core generated by Xilinx and add 2 wishbone slaves |
20-08-2010 | Test the core on SP605 dev kit, along with the FMC-ADC-100M-14b-4cha |