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FMC DEL 1ns 4cha
Commit 2e42bef3 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge branch '28-improve-dcr_enable-timing' into 'master' 

Resolve "Improve dcr_enable timing"

Closes #28

See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!16
parents ab8edc42 f354a5d6
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Showing with 15 additions and 46 deletions
.gitlab-ci.yml
View file @ 2e42bef3
...@@ -12,7 +12,6 @@ include: ...@@ -12,7 +12,6 @@ include:
ref: master ref: master
file: file:
- 'edl-gitlab-ci.yml' - 'edl-gitlab-ci.yml'
- local: 'hdl/syn/.gitlab-ci.yml'
cppcheck: cppcheck:
stage: analyse stage: analyse
...@@ -40,3 +39,12 @@ kernel_build_validation: ...@@ -40,3 +39,12 @@ kernel_build_validation:
echo "Checking Dependencies" echo "Checking Dependencies"
if [ "$FMC_BUILDS" != "0" ]; then echo 'FMC did not build successfully. Exiting'; exit 1; fi if [ "$FMC_BUILDS" != "0" ]; then echo 'FMC did not build successfully. Exiting'; exit 1; fi
if [ "$ZIO_BUILDS" != "0" ]; then echo 'ZIO did not build successfully. Exiting'; exit 1; fi if [ "$ZIO_BUILDS" != "0" ]; then echo 'ZIO did not build successfully. Exiting'; exit 1; fi
fpga_synthesis:
extends: .synthesis-ise-14-7
interruptible: true
parallel:
matrix:
- EDL_CI_SYN_SRC_PATH:
- hdl/syn/spec
- hdl/syn/svec
hdl/rtl/fd_delay_channel_driver.vhd
View file @ 2e42bef3
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2014-03-24 -- Last update: 2023-10-26
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -194,6 +194,7 @@ architecture behavioral of fd_delay_channel_driver is ...@@ -194,6 +194,7 @@ architecture behavioral of fd_delay_channel_driver is
signal tag_valid_d : std_logic_vector(4 downto 0); signal tag_valid_d : std_logic_vector(4 downto 0);
signal dcr_arm_d : std_logic_vector(4 downto 0); signal dcr_arm_d : std_logic_vector(4 downto 0);
signal dcr_en_d : std_logic;
signal regs_in : t_fd_channel_out_registers; signal regs_in : t_fd_channel_out_registers;
signal regs_out : t_fd_channel_in_registers; signal regs_out : t_fd_channel_in_registers;
...@@ -228,9 +229,11 @@ begin ...@@ -228,9 +229,11 @@ begin
if rst_n_ref_i = '0' then if rst_n_ref_i = '0' then
tag_valid_d <= (others => '0'); tag_valid_d <= (others => '0');
dcr_arm_d <= (others => '0'); dcr_arm_d <= (others => '0');
dcr_en_d <= '0';
else else
tag_valid_d <= tag_valid_d(tag_valid_d'length-2 downto 0) & tag_valid_i; tag_valid_d <= tag_valid_d(tag_valid_d'length-2 downto 0) & tag_valid_i;
dcr_arm_d <= dcr_arm_d(dcr_arm_d'length-2 downto 0) & regs_in.dcr_pg_arm_o; dcr_arm_d <= dcr_arm_d(dcr_arm_d'length-2 downto 0) & regs_in.dcr_pg_arm_o;
dcr_en_d <= regs_in.dcr_enable_o;
end if; end if;
end if; end if;
end process; end process;
...@@ -393,7 +396,7 @@ begin ...@@ -393,7 +396,7 @@ begin
p_match_hit_stage1 : process(clk_ref_i) p_match_hit_stage1 : process(clk_ref_i)
begin begin
if rising_edge(clk_ref_i) then if rising_edge(clk_ref_i) then
if rst_n_ref_i = '0' or regs_in.dcr_enable_o = '0' then if rst_n_ref_i = '0' or dcr_en_d = '0' then
hit_end <= '0'; hit_end <= '0';
hit_start <= '0'; hit_start <= '0';
hit_start_stage1 <= (others => '0'); hit_start_stage1 <= (others => '0');
...@@ -421,7 +424,7 @@ begin ...@@ -421,7 +424,7 @@ begin
p_fine_fsm : process(clk_ref_i) p_fine_fsm : process(clk_ref_i)
begin begin
if rising_edge(clk_ref_i) then if rising_edge(clk_ref_i) then
if rst_n_ref_i = '0' or regs_in.dcr_enable_o = '0' then if rst_n_ref_i = '0' or dcr_en_d = '0' then
state <= IDLE; state <= IDLE;
delay_load_o <= '0'; delay_load_o <= '0';
first_pulse <= '1'; first_pulse <= '1';
......
hdl/syn/.gitlab-ci.yml deleted 100644 → 0
View file @ ab8edc42
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
variables:
_FMC_DELAY_BITSTREAM_DEST: $CI_PROJECT_DIR/$EDL_CI_EOS_OUTPUT_DIR/bitstreams
.syn_template: &syn_template
interruptible: true
stage: build
needs: []
tags:
- xilinx_ise
- "14.7"
script:
- git submodule init && git submodule update
- cd hdl/syn/"$SYN_NAME"/
- hdlmake
- make
- |
if [[ $(cat *.par | grep -c "All constraints were met") = 0 ]]
then
echo -e "\e[31mTiming errors detected in PAR report. Aborting...\e[0m"
exit 1
fi
- tar -cJf $SYN_NAME.tar.xz *.syr *.par *.twr *.bit *.bin
- mkdir -p $_FMC_DELAY_BITSTREAM_DEST
- cp $SYN_NAME.tar.xz $_FMC_DELAY_BITSTREAM_DEST
artifacts:
name: "$SYN_NAME-synthesis-$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
paths:
- $_FMC_DELAY_BITSTREAM_DEST/*
SPEC synthesis:
variables:
SYN_NAME: "spec"
<<: *syn_template
SVEC synthesis:
variables:
SYN_NAME: "svec"
<<: *syn_template
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