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VME FMC Carrier VFC
Commit cb70c6e4 authored by Andrea Boccardi's avatar Andrea Boccardi
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corrected error in the ucf file

parent dccb0d8b
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Showing with 32833 additions and 33299 deletions
trunk/firmware/XilinxISE/SystemFpga/SFpga.bld
View file @ cb70c6e4
...@@ -12,13 +12,28 @@ Done. ...@@ -12,13 +12,28 @@ Done.
Annotating constraints to design from ucf file "SFpga.ucf" ... Annotating constraints to design from ucf file "SFpga.ucf" ...
Resolving constraint associations... Resolving constraint associations...
Checking Constraint Associations... Checking Constraint Associations...
WARNING:ConstraintSystem:137 - Constraint <NET "VcTcXo_ik" TNM_NET = VcTcXo_ik;>
[SFpga.ucf(701)]: No appropriate instances for the TNM constraint are driven
by "VcTcXo_ik".
WARNING:ConstraintSystem:137 - Constraint <NET "VmeSysClk_ik" TNM_NET =
VmeSysClk_ik;> [SFpga.ucf(702)]: No appropriate instances for the TNM
constraint are driven by "VmeSysClk_ik".
WARNING:ConstraintSystem:194 - The TNM 'VcTcXo_ik', does not directly or
indirectly drive any flip-flops, latches and/or RAMs and is not actively used
by any referencing constraint.
WARNING:ConstraintSystem:194 - The TNM 'VmeSysClk_ik', does not directly or
indirectly drive any flip-flops, latches and/or RAMs and is not actively used
by any referencing constraint.
Done... Done...
Checking expanded design ... Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N452' has no driver
WARNING:NgdBuild:452 - logical net 'N454' has no driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TempIdDQ_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<3>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<3>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<2>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<2>' has no legal driver
...@@ -28,7 +43,8 @@ WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgClk_io' has no legal driver ...@@ -28,7 +43,8 @@ WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgClk_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgCsi_io' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgCsi_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgRdWr_io' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgRdWr_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgInit_io' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgInit_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TempIdDQ_io' has no legal driver WARNING:NgdBuild:452 - logical net 'N504' has no driver
WARNING:NgdBuild:452 - logical net 'N506' has no driver
Partition Implementation Status Partition Implementation Status
------------------------------- -------------------------------
...@@ -39,9 +55,9 @@ Partition Implementation Status ...@@ -39,9 +55,9 @@ Partition Implementation Status
NGDBUILD Design Results Summary: NGDBUILD Design Results Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 14 Number of warnings: 18
Total memory usage is 155532 kilobytes Total memory usage is 150888 kilobytes
Writing NGD file "SFpga.ngd" ... Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec Total REAL time to NGDBUILD completion: 3 sec
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.cmd_log
View file @ cb70c6e4
...@@ -110,3 +110,80 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 - ...@@ -110,3 +110,80 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
trunk/firmware/XilinxISE/SystemFpga/SFpga.ncd
View file @ cb70c6e4
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ngc
View file @ cb70c6e4
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ngd
View file @ cb70c6e4
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ngr
View file @ cb70c6e4
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.pad
View file @ cb70c6e4
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 17:36:28 2010 Thu Jan 06 13:57:44 2011
# NOTE: This file is designed to be imported into a spreadsheet program # NOTE: This file is designed to be imported into a spreadsheet program
...@@ -543,7 +543,7 @@ R1||IOBS|IO_L44N_GCLK20_M3A6_3|UNUSED||3||||||||| ...@@ -543,7 +543,7 @@ R1||IOBS|IO_L44N_GCLK20_M3A6_3|UNUSED||3|||||||||
R2||IOBM|IO_L44P_GCLK21_M3A5_3|UNUSED||3||||||||| R2||IOBM|IO_L44P_GCLK21_M3A5_3|UNUSED||3|||||||||
R3|FpLed_onb8<2>|IOB|IO_L52N_M3A9_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE| R3|FpLed_onb8<2>|IOB|IO_L52N_M3A9_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R4|FpLed_onb8<1>|IOB|IO_L52P_M3A8_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE| R4|FpLed_onb8<1>|IOB|IO_L52P_M3A8_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R5|FpLed_onb8<4>|IOB|IO_L50N_M3BA2_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE| R5|FpLed_onb8<4>|IOB|IO_L50N_M3BA2_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R6|SysAppClk_ik|IOB|IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| R6|SysAppClk_ik|IOB|IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
R7|SysAppClk_ok|IOB|IO_L43P_GCLK23_M3RASN_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE| R7|SysAppClk_ok|IOB|IO_L43P_GCLK23_M3RASN_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R8|ManualAddress_ib5<0>|IOB|IO_L45P_M3A3_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| R8|ManualAddress_ib5<0>|IOB|IO_L45P_M3A3_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
...@@ -593,7 +593,7 @@ T25|||VCCO_1|||1|||||1.50|||| ...@@ -593,7 +593,7 @@ T25|||VCCO_1|||1|||||1.50||||
T26||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1||||||||| T26||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1|||||||||
U1|Fmc2PrsntM2C_in|IOB|IO_L40N_M3DQ7_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| U1|Fmc2PrsntM2C_in|IOB|IO_L40N_M3DQ7_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
U2|Fmc2PGC2M_in|IOB|IO_L40P_M3DQ6_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE| U2|Fmc2PGC2M_in|IOB|IO_L40P_M3DQ6_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U3|FpLed_onb8<5>|IOB|IO_L10N_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE| U3|FpLed_onb8<5>|IOB|IO_L10N_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U4|FpLed_onb8<6>|IOB|IO_L10P_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE| U4|FpLed_onb8<6>|IOB|IO_L10P_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U5|AFpgaProgD_iob8<4>|IOB|IO_L46P_M3CLK_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| U5|AFpgaProgD_iob8<4>|IOB|IO_L46P_M3CLK_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
U6|||VCCAUX||||||||2.5|||| U6|||VCCAUX||||||||2.5||||
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.par
View file @ cb70c6e4
Release 12.3 par M.70d (nt64) Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PCBE13225:: Mon Dec 20 17:35:53 2010 PCBE13225:: Thu Jan 06 13:57:13 2011
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
...@@ -21,16 +21,16 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15". ...@@ -21,16 +21,16 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary: Device Utilization Summary:
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 834 out of 184,304 1% Number of Slice Registers: 784 out of 184,304 1%
Number used as Flip Flops: 834 Number used as Flip Flops: 784
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 965 out of 92,152 1% Number of Slice LUTs: 878 out of 92,152 1%
Number used as logic: 934 out of 92,152 1% Number used as logic: 851 out of 92,152 1%
Number using O6 output only: 579 Number using O6 output only: 622
Number using O5 output only: 187 Number using O5 output only: 83
Number using O5 and O6: 168 Number using O5 and O6: 146
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1% Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
...@@ -39,20 +39,20 @@ Slice Logic Utilization: ...@@ -39,20 +39,20 @@ Slice Logic Utilization:
Number using O5 and O6: 4 Number using O5 and O6: 4
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 6 Number used as Shift Register: 6
Number using O6 output only: 6 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 2
Number used exclusively as route-thrus: 17 Number used exclusively as route-thrus: 13
Number with same-slice register load: 7 Number with same-slice register load: 8
Number with same-slice carry load: 10 Number with same-slice carry load: 5
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 383 out of 23,038 1% Number of occupied Slices: 353 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,137 Number of LUT Flip Flop pairs used: 1,041
Number with an unused Flip Flop: 369 out of 1,137 32% Number with an unused Flip Flop: 330 out of 1,041 31%
Number with an unused LUT: 172 out of 1,137 15% Number with an unused LUT: 163 out of 1,041 15%
Number of fully used LUT-FF pairs: 596 out of 1,137 52% Number of fully used LUT-FF pairs: 548 out of 1,041 52%
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0% to control set restrictions: 0 out of 184,304 0%
...@@ -73,8 +73,8 @@ Specific Feature Utilization: ...@@ -73,8 +73,8 @@ Specific Feature Utilization:
Number of RAMB8BWERs: 0 out of 536 0% Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25% Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 4 Number used as BUFGs: 2
Number used as BUFGMUX: 0 Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0% Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0% Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
...@@ -99,11 +99,11 @@ Specific Feature Utilization: ...@@ -99,11 +99,11 @@ Specific Feature Utilization:
Overall effort level (-ol): High Overall effort level (-ol): High
Router effort level (-rl): High Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 10 secs Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs Finished initial Timing Analysis. REAL time: 10 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsRamSwpOvr_i_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal DdsRamSwpOvr_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal PcbRev_ib8<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal PcbRev_ib8<1>_IBUF has no load. PAR will not attempt to route this signal.
...@@ -127,6 +127,7 @@ WARNING:Par:288 - The signal WRTxFault_i_IBUF has no load. PAR will not attempt ...@@ -127,6 +127,7 @@ WARNING:Par:288 - The signal WRTxFault_i_IBUF has no load. PAR will not attempt
WARNING:Par:288 - The signal AFpgaProgClk_io_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgClk_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeAm_ib6<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal VmeAm_ib6<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeAm_ib6<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal VmeAm_ib6<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeSysClk_ik_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgRdWr_io_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgRdWr_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal Sfp2TxFault_i_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal Sfp2TxFault_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgD_iob8<0>_IBUF has no load. PAR will not attempt to route this signal.
...@@ -142,6 +143,7 @@ WARNING:Par:288 - The signal DdsDrOver_i_IBUF has no load. PAR will not attempt ...@@ -142,6 +143,7 @@ WARNING:Par:288 - The signal DdsDrOver_i_IBUF has no load. PAR will not attempt
WARNING:Par:288 - The signal AFpgaProgM_iob2<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgM_iob2<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsPdClk_ik_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal DdsPdClk_ik_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VcTcXo_ik_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal WRLoS_i_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal WRLoS_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsSyncSmpErr_i_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal DdsSyncSmpErr_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeTdi_i_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal VmeTdi_i_IBUF has no load. PAR will not attempt to route this signal.
...@@ -155,29 +157,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O ...@@ -155,29 +157,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router Starting Router
Phase 1 : 5283 unrouted; REAL time: 12 secs Phase 1 : 4878 unrouted; REAL time: 11 secs
Phase 2 : 4622 unrouted; REAL time: 16 secs Phase 2 : 4344 unrouted; REAL time: 15 secs
Phase 3 : 1786 unrouted; REAL time: 24 secs Phase 3 : 1688 unrouted; REAL time: 21 secs
Phase 4 : 1786 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs Phase 4 : 1688 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs
Updating file: SFpga.ncd with current fully routed design. Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Total REAL time to Router completion: 32 secs Total REAL time to Router completion: 29 secs
Total CPU time to Router completion: 30 secs Total CPU time to Router completion: 29 secs
Partition Implementation Status Partition Implementation Status
------------------------------- -------------------------------
...@@ -195,20 +197,12 @@ Generating Clock Report ...@@ -195,20 +197,12 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_IBUF_BUFG | BUFGMUX_X3Y16| No | 210 | 0.329 | 1.697 | | Si57x_BUFG | BUFGMUX_X2Y4| No | 218 | 0.316 | 1.696 |
+---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 6 | 0.008 | 1.686 |
+---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y10| No | 6 | 0.084 | 1.639 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.188 | 1.690 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 197 | 0.000 | 3.235 | | SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.057 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+
| i_Core/WriteCycle | Local| | 1 | 0.000 | 2.542 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | | |i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 4.912 | | e/Stb_oq | Local| | 18 | 0.000 | 1.316 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing * Net Skew is the difference between the minimum and maximum routing
...@@ -227,22 +221,14 @@ Asterisk (*) preceding a constraint indicates it was not met. ...@@ -227,22 +221,14 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score | | Slack | Achievable | Errors | Score
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 5.091ns| 4.909ns| 0| 0 TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" | SETUP | 0.331ns| 8.002ns| 0| 0
lk_ik" 100 MHz HIGH 50% | HOLD | 0.482ns| | 0| 0 120 MHz HIGH 50% | HOLD | 0.374ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | MINPERIOD | 7.500ns| 2.500ns| 0| 0
00 MHz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" | SETUP | 7.730ns| 2.270ns| 0| 0
100 MHz HIGH 50% | HOLD | 0.521ns| | 0| 0
| MINPERIOD | 7.500ns| 2.500ns| 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_VmeSysClk_ik = PERIOD TIMEGRP "VmeSysC | SETUP | 22.874ns| 2.126ns| 0| 0 TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 3.723ns| 4.610ns| 0| 0
lk_ik" 40 MHz HIGH 50% | HOLD | 0.521ns| | 0| 0 lk_ik" 120 MHz HIGH 50% | HOLD | 0.482ns| | 0| 0
| MINPERIOD | 22.500ns| 2.500ns| 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_VcTcXo_ik = PERIOD TIMEGRP "VcTcXo_ik" | SETUP | 27.265ns| 12.735ns| 0| 0 TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | MINPERIOD | 5.833ns| 2.500ns| 0| 0
25 MHz HIGH 50% | HOLD | 0.413ns| | 0| 0 20 MHz HIGH 50% | | | | |
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
...@@ -255,10 +241,10 @@ All signals are completely routed. ...@@ -255,10 +241,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 50 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. WARNING:Par:283 - There are 50 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 35 secs Total REAL time to PAR completion: 31 secs
Total CPU time to PAR completion: 33 secs Total CPU time to PAR completion: 31 secs
Peak Memory Usage: 572 MB Peak Memory Usage: 544 MB
Placer: Placement generated during map. Placer: Placement generated during map.
Routing: Completed - No errors found. Routing: Completed - No errors found.
...@@ -266,7 +252,7 @@ Timing: Completed - No errors found. ...@@ -266,7 +252,7 @@ Timing: Completed - No errors found.
Number of error messages: 0 Number of error messages: 0
Number of warning messages: 52 Number of warning messages: 52
Number of info messages: 0 Number of info messages: 1
Writing design to file SFpga.ncd Writing design to file SFpga.ncd
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.pcf
View file @ cb70c6e4
//! ************************************************************************** //! **************************************************************************
// Written by: Map M.70d on Mon Dec 20 17:35:51 2010 // Written by: Map M.70d on Thu Jan 06 13:57:10 2011
//! ************************************************************************** //! **************************************************************************
SCHEMATIC START; SCHEMATIC START;
...@@ -46,8 +46,8 @@ COMP "DdrCkE_o" LOCATE = SITE "N21" LEVEL 1; ...@@ -46,8 +46,8 @@ COMP "DdrCkE_o" LOCATE = SITE "N21" LEVEL 1;
COMP "PllFmc2Ref1_ok" LOCATE = SITE "Y12" LEVEL 1; COMP "PllFmc2Ref1_ok" LOCATE = SITE "Y12" LEVEL 1;
COMP "DdrUDM_o" LOCATE = SITE "V23" LEVEL 1; COMP "DdrUDM_o" LOCATE = SITE "V23" LEVEL 1;
COMP "PllFmc2Sdo_i" LOCATE = SITE "V14" LEVEL 1; COMP "PllFmc2Sdo_i" LOCATE = SITE "V14" LEVEL 1;
COMP "VmeDs_inb2<1>" LOCATE = SITE "G20" LEVEL 1;
COMP "PllSysSdo_i" LOCATE = SITE "AF6" LEVEL 1; COMP "PllSysSdo_i" LOCATE = SITE "AF6" LEVEL 1;
COMP "VmeDs_inb2<1>" LOCATE = SITE "G20" LEVEL 1;
COMP "VmeDs_inb2<2>" LOCATE = SITE "H20" LEVEL 1; COMP "VmeDs_inb2<2>" LOCATE = SITE "H20" LEVEL 1;
COMP "VmeIrq_ob7<1>" LOCATE = SITE "L7" LEVEL 1; COMP "VmeIrq_ob7<1>" LOCATE = SITE "L7" LEVEL 1;
COMP "VmeIrq_ob7<2>" LOCATE = SITE "J7" LEVEL 1; COMP "VmeIrq_ob7<2>" LOCATE = SITE "J7" LEVEL 1;
...@@ -280,8 +280,8 @@ COMP "WRTxDisable_o" LOCATE = SITE "K5" LEVEL 1; ...@@ -280,8 +280,8 @@ COMP "WRTxDisable_o" LOCATE = SITE "K5" LEVEL 1;
COMP "ManualAddress_ib5<4>" LOCATE = SITE "P10" LEVEL 1; COMP "ManualAddress_ib5<4>" LOCATE = SITE "P10" LEVEL 1;
COMP "PllFmc2RefSel_o" LOCATE = SITE "V13" LEVEL 1; COMP "PllFmc2RefSel_o" LOCATE = SITE "V13" LEVEL 1;
COMP "FlashAFpgaQ_i" LOCATE = SITE "AA18" LEVEL 1; COMP "FlashAFpgaQ_i" LOCATE = SITE "AA18" LEVEL 1;
COMP "PllFmc1Reset_orn" LOCATE = SITE "AC5" LEVEL 1;
COMP "VcTcXo_ik" LOCATE = SITE "AF14" LEVEL 1; COMP "VcTcXo_ik" LOCATE = SITE "AF14" LEVEL 1;
COMP "PllFmc1Reset_orn" LOCATE = SITE "AC5" LEVEL 1;
COMP "SysAppClk_ok" LOCATE = SITE "R7" LEVEL 1; COMP "SysAppClk_ok" LOCATE = SITE "R7" LEVEL 1;
COMP "WRLoS_i" LOCATE = SITE "L6" LEVEL 1; COMP "WRLoS_i" LOCATE = SITE "L6" LEVEL 1;
COMP "PllSysRefMon_i" LOCATE = SITE "AD14" LEVEL 1; COMP "PllSysRefMon_i" LOCATE = SITE "AD14" LEVEL 1;
...@@ -334,109 +334,113 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1; ...@@ -334,109 +334,113 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1;
COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1; COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1;
COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1; COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1;
COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1; COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1;
TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/VcTcXoDivider_c_22" BEL "i_Core/VcTcXoDivider_c_21" BEL "i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/VcTcXoDivider_c_20" BEL "i_Core/VcTcXoDivider_c_19" BEL "i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/VcTcXoDivider_c_18" BEL "i_Core/VcTcXoDivider_c_17" BEL "i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/VcTcXoDivider_c_16" BEL "i_Core/VcTcXoDivider_c_15" BEL "i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
"i_Core/VcTcXoDivider_c_14" BEL "i_Core/VcTcXoDivider_c_13" BEL "i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL
"i_Core/VcTcXoDivider_c_12" BEL "i_Core/VcTcXoDivider_c_11" BEL "i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL
"i_Core/VcTcXoDivider_c_10" BEL "i_Core/VcTcXoDivider_c_9" BEL "i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL
"i_Core/VcTcXoDivider_c_8" BEL "i_Core/VcTcXoDivider_c_7" BEL "i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL
"i_Core/VcTcXoDivider_c_6" BEL "i_Core/VcTcXoDivider_c_5" BEL "i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/VcTcXoDivider_c_4" BEL "i_Core/VcTcXoDivider_c_3" BEL "i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/VcTcXoDivider_c_2" BEL "i_Core/VcTcXoDivider_c_1" BEL "i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/VcTcXoDivider_c_0" BEL "i_Core/Rst_rq" BEL "i_Core/Si57xDivider_c_0" BEL "i_Core/Rst_rq" BEL
"i_Core/i_VmeInterface/state_FSM_FFd2" BEL "i_Core/i_VmeInterface/State_q_FSM_FFd2" BEL
"i_Core/i_VmeInterface/stb_d" BEL "i_Core/i_VmeInterface/adr_o_21" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_29" BEL
"i_Core/i_VmeInterface/adr_o_20" BEL "i_Core/i_VmeInterface/adr_o_19" "i_Core/i_VmeInterface/TimoutCounter_cb30_28" BEL
BEL "i_Core/i_VmeInterface/adr_o_18" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_27" BEL
"i_Core/i_VmeInterface/adr_o_17" BEL "i_Core/i_VmeInterface/adr_o_16" "i_Core/i_VmeInterface/TimoutCounter_cb30_26" BEL
BEL "i_Core/i_VmeInterface/adr_o_15" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_25" BEL
"i_Core/i_VmeInterface/adr_o_14" BEL "i_Core/i_VmeInterface/adr_o_13" "i_Core/i_VmeInterface/TimoutCounter_cb30_24" BEL
BEL "i_Core/i_VmeInterface/adr_o_12" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_23" BEL
"i_Core/i_VmeInterface/adr_o_11" BEL "i_Core/i_VmeInterface/adr_o_10" "i_Core/i_VmeInterface/TimoutCounter_cb30_22" BEL
BEL "i_Core/i_VmeInterface/adr_o_9" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_21" BEL
"i_Core/i_VmeInterface/adr_o_8" BEL "i_Core/i_VmeInterface/adr_o_7" "i_Core/i_VmeInterface/TimoutCounter_cb30_20" BEL
BEL "i_Core/i_VmeInterface/adr_o_6" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_19" BEL
"i_Core/i_VmeInterface/adr_o_5" BEL "i_Core/i_VmeInterface/adr_o_4" "i_Core/i_VmeInterface/TimoutCounter_cb30_18" BEL
BEL "i_Core/i_VmeInterface/adr_o_3" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_17" BEL
"i_Core/i_VmeInterface/adr_o_2" BEL "i_Core/i_VmeInterface/adr_o_1" "i_Core/i_VmeInterface/TimoutCounter_cb30_16" BEL
BEL "i_Core/i_VmeInterface/adr_o_0" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_15" BEL
"i_Core/i_VmeInterface/vme_dtack" BEL "i_Core/i_VmeInterface/VmeDOe_o" "i_Core/i_VmeInterface/TimoutCounter_cb30_14" BEL
BEL "i_Core/i_VmeInterface/dat_o_31" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_13" BEL
"i_Core/i_VmeInterface/dat_o_30" BEL "i_Core/i_VmeInterface/dat_o_29" "i_Core/i_VmeInterface/TimoutCounter_cb30_12" BEL
BEL "i_Core/i_VmeInterface/dat_o_28" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_11" BEL
"i_Core/i_VmeInterface/dat_o_27" BEL "i_Core/i_VmeInterface/dat_o_26" "i_Core/i_VmeInterface/TimoutCounter_cb30_10" BEL
BEL "i_Core/i_VmeInterface/dat_o_25" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_9" BEL
"i_Core/i_VmeInterface/dat_o_24" BEL "i_Core/i_VmeInterface/dat_o_23" "i_Core/i_VmeInterface/TimoutCounter_cb30_8" BEL
BEL "i_Core/i_VmeInterface/dat_o_22" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_7" BEL
"i_Core/i_VmeInterface/dat_o_21" BEL "i_Core/i_VmeInterface/dat_o_20" "i_Core/i_VmeInterface/TimoutCounter_cb30_6" BEL
BEL "i_Core/i_VmeInterface/dat_o_19" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_5" BEL
"i_Core/i_VmeInterface/dat_o_18" BEL "i_Core/i_VmeInterface/dat_o_17" "i_Core/i_VmeInterface/TimoutCounter_cb30_4" BEL
BEL "i_Core/i_VmeInterface/dat_o_16" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_3" BEL
"i_Core/i_VmeInterface/dat_o_15" BEL "i_Core/i_VmeInterface/dat_o_14" "i_Core/i_VmeInterface/TimoutCounter_cb30_2" BEL
BEL "i_Core/i_VmeInterface/dat_o_13" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_1" BEL
"i_Core/i_VmeInterface/dat_o_12" BEL "i_Core/i_VmeInterface/dat_o_11" "i_Core/i_VmeInterface/TimoutCounter_cb30_0" BEL
BEL "i_Core/i_VmeInterface/dat_o_10" BEL "i_Core/i_VmeInterface/State_q_FSM_FFd1" BEL
"i_Core/i_VmeInterface/dat_o_9" BEL "i_Core/i_VmeInterface/dat_o_8" "i_Core/i_VmeInterface/Dat_obq32_31" BEL
BEL "i_Core/i_VmeInterface/dat_o_7" BEL "i_Core/i_VmeInterface/Dat_obq32_30" BEL
"i_Core/i_VmeInterface/dat_o_6" BEL "i_Core/i_VmeInterface/dat_o_5" "i_Core/i_VmeInterface/Dat_obq32_29" BEL
BEL "i_Core/i_VmeInterface/dat_o_4" BEL "i_Core/i_VmeInterface/Dat_obq32_28" BEL
"i_Core/i_VmeInterface/dat_o_3" BEL "i_Core/i_VmeInterface/dat_o_2" "i_Core/i_VmeInterface/Dat_obq32_27" BEL
BEL "i_Core/i_VmeInterface/dat_o_1" BEL "i_Core/i_VmeInterface/Dat_obq32_26" BEL
"i_Core/i_VmeInterface/dat_o_0" BEL "i_Core/i_VmeInterface/vme_irqn_7" "i_Core/i_VmeInterface/Dat_obq32_25" BEL
BEL "i_Core/i_VmeInterface/vme_irqn_6" BEL "i_Core/i_VmeInterface/Dat_obq32_24" BEL
"i_Core/i_VmeInterface/vme_irqn_5" BEL "i_Core/i_VmeInterface/Dat_obq32_23" BEL
"i_Core/i_VmeInterface/vme_irqn_4" BEL "i_Core/i_VmeInterface/Dat_obq32_22" BEL
"i_Core/i_VmeInterface/vme_irqn_3" BEL "i_Core/i_VmeInterface/Dat_obq32_21" BEL
"i_Core/i_VmeInterface/vme_irqn_2" BEL "i_Core/i_VmeInterface/Dat_obq32_20" BEL
"i_Core/i_VmeInterface/vme_irqn_1" BEL "i_Core/i_VmeInterface/Dat_obq32_19" BEL
"i_Core/i_VmeInterface/as_shr_1" BEL "i_Core/i_VmeInterface/as_shr_0" "i_Core/i_VmeInterface/Dat_obq32_18" BEL
BEL "i_Core/i_VmeInterface/VmeBaseAddr_7" BEL "i_Core/i_VmeInterface/Dat_obq32_17" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_6" BEL "i_Core/i_VmeInterface/Dat_obq32_16" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_5" BEL "i_Core/i_VmeInterface/Dat_obq32_15" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_4" BEL "i_Core/i_VmeInterface/Dat_obq32_14" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_3" BEL "i_Core/i_VmeInterface/Dat_obq32_13" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_2" BEL "i_Core/i_VmeInterface/Dat_obq32_12" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_1" BEL "i_Core/i_VmeInterface/Dat_obq32_11" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_0" BEL "i_Core/i_VmeInterface/Dat_obq32_10" BEL
"i_Core/i_VmeInterface/VmeDDirFpgaToVme_o" BEL "i_Core/i_VmeInterface/Dat_obq32_9" BEL
"i_Core/i_VmeInterface/SendIrqVector" BEL "i_Core/i_VmeInterface/Dat_obq32_8" BEL
"i_Core/i_VmeInterface/clear_int" BEL "i_Core/i_VmeInterface/we_o" BEL "i_Core/i_VmeInterface/Dat_obq32_7" BEL
"i_Core/i_VmeInterface/ack_d" BEL "i_Core/i_VmeInterface/oe_vme_data" "i_Core/i_VmeInterface/Dat_obq32_6" BEL
BEL "i_Core/i_VmeInterface/DataReg_31" BEL "i_Core/i_VmeInterface/Dat_obq32_5" BEL
"i_Core/i_VmeInterface/DataReg_30" BEL "i_Core/i_VmeInterface/Dat_obq32_4" BEL
"i_Core/i_VmeInterface/DataReg_29" BEL "i_Core/i_VmeInterface/Dat_obq32_3" BEL
"i_Core/i_VmeInterface/DataReg_28" BEL "i_Core/i_VmeInterface/Dat_obq32_2" BEL
"i_Core/i_VmeInterface/DataReg_27" BEL "i_Core/i_VmeInterface/Dat_obq32_1" BEL
"i_Core/i_VmeInterface/DataReg_26" BEL "i_Core/i_VmeInterface/Dat_obq32_0" BEL
"i_Core/i_VmeInterface/DataReg_25" BEL "i_Core/i_VmeInterface/VmeDtAck_oqn" BEL
"i_Core/i_VmeInterface/DataReg_24" BEL "i_Core/i_VmeInterface/Adr_obq22_21" BEL
"i_Core/i_VmeInterface/DataReg_23" BEL "i_Core/i_VmeInterface/Adr_obq22_20" BEL
"i_Core/i_VmeInterface/DataReg_22" BEL "i_Core/i_VmeInterface/Adr_obq22_19" BEL
"i_Core/i_VmeInterface/DataReg_21" BEL "i_Core/i_VmeInterface/Adr_obq22_18" BEL
"i_Core/i_VmeInterface/DataReg_20" BEL "i_Core/i_VmeInterface/Adr_obq22_17" BEL
"i_Core/i_VmeInterface/DataReg_19" BEL "i_Core/i_VmeInterface/Adr_obq22_16" BEL
"i_Core/i_VmeInterface/DataReg_18" BEL "i_Core/i_VmeInterface/Adr_obq22_15" BEL
"i_Core/i_VmeInterface/DataReg_17" BEL "i_Core/i_VmeInterface/Adr_obq22_14" BEL
"i_Core/i_VmeInterface/DataReg_16" BEL "i_Core/i_VmeInterface/Adr_obq22_13" BEL
"i_Core/i_VmeInterface/DataReg_15" BEL "i_Core/i_VmeInterface/Adr_obq22_12" BEL
"i_Core/i_VmeInterface/DataReg_14" BEL "i_Core/i_VmeInterface/Adr_obq22_11" BEL
"i_Core/i_VmeInterface/DataReg_13" BEL "i_Core/i_VmeInterface/Adr_obq22_10" BEL
"i_Core/i_VmeInterface/DataReg_12" BEL "i_Core/i_VmeInterface/Adr_obq22_9" BEL
"i_Core/i_VmeInterface/DataReg_11" BEL "i_Core/i_VmeInterface/Adr_obq22_8" BEL
"i_Core/i_VmeInterface/DataReg_10" BEL "i_Core/i_VmeInterface/Adr_obq22_7" BEL
"i_Core/i_VmeInterface/DataReg_9" BEL "i_Core/i_VmeInterface/Adr_obq22_6" BEL
"i_Core/i_VmeInterface/DataReg_8" BEL "i_Core/i_VmeInterface/Adr_obq22_5" BEL
"i_Core/i_VmeInterface/DataReg_7" BEL "i_Core/i_VmeInterface/Adr_obq22_4" BEL
"i_Core/i_VmeInterface/DataReg_6" BEL "i_Core/i_VmeInterface/Adr_obq22_3" BEL
"i_Core/i_VmeInterface/DataReg_5" BEL "i_Core/i_VmeInterface/Adr_obq22_2" BEL
"i_Core/i_VmeInterface/DataReg_4" BEL "i_Core/i_VmeInterface/Adr_obq22_1" BEL
"i_Core/i_VmeInterface/DataReg_3" BEL "i_Core/i_VmeInterface/Adr_obq22_0" BEL
"i_Core/i_VmeInterface/DataReg_2" BEL "i_Core/i_VmeInterface/VmeIrqn_oqnb7_7" BEL
"i_Core/i_VmeInterface/DataReg_1" BEL "i_Core/i_VmeInterface/VmeIrqn_oqnb7_6" BEL
"i_Core/i_VmeInterface/DataReg_0" BEL "i_Core/i_VmeInterface/VmeIrqn_oqnb7_5" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_4" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_3" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_2" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_22" BEL "i_Core/i_VmeAccessMonostable/Counter_c_22" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_21" BEL "i_Core/i_VmeAccessMonostable/Counter_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_20" BEL "i_Core/i_VmeAccessMonostable/Counter_c_20" BEL
...@@ -461,54 +465,6 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL ...@@ -461,54 +465,6 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_1" BEL "i_Core/i_VmeAccessMonostable/Counter_c_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_0" BEL "i_Core/i_VmeAccessMonostable/Counter_c_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL "i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_ClearMonostable/Counter_c_22" BEL
"i_Core/i_ClearMonostable/Counter_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_20" BEL
"i_Core/i_ClearMonostable/Counter_c_19" BEL
"i_Core/i_ClearMonostable/Counter_c_18" BEL
"i_Core/i_ClearMonostable/Counter_c_17" BEL
"i_Core/i_ClearMonostable/Counter_c_16" BEL
"i_Core/i_ClearMonostable/Counter_c_15" BEL
"i_Core/i_ClearMonostable/Counter_c_14" BEL
"i_Core/i_ClearMonostable/Counter_c_13" BEL
"i_Core/i_ClearMonostable/Counter_c_12" BEL
"i_Core/i_ClearMonostable/Counter_c_11" BEL
"i_Core/i_ClearMonostable/Counter_c_10" BEL
"i_Core/i_ClearMonostable/Counter_c_9" BEL
"i_Core/i_ClearMonostable/Counter_c_8" BEL
"i_Core/i_ClearMonostable/Counter_c_7" BEL
"i_Core/i_ClearMonostable/Counter_c_6" BEL
"i_Core/i_ClearMonostable/Counter_c_5" BEL
"i_Core/i_ClearMonostable/Counter_c_4" BEL
"i_Core/i_ClearMonostable/Counter_c_3" BEL
"i_Core/i_ClearMonostable/Counter_c_2" BEL
"i_Core/i_ClearMonostable/Counter_c_1" BEL
"i_Core/i_ClearMonostable/Counter_c_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_22" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_21" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_20" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_19" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_18" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_17" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_16" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_15" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_14" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_13" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_12" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_11" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_10" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_9" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_8" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_7" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_6" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_5" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_4" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_3" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_2" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_1" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_0" BEL
"i_Core/i_WriteCycleMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_Debouncer/Counter_c_15" BEL "i_Core/i_Debouncer/Counter_c_15" BEL
"i_Core/i_Debouncer/Counter_c_14" BEL "i_Core/i_Debouncer/Counter_c_14" BEL
"i_Core/i_Debouncer/Counter_c_13" BEL "i_Core/i_Debouncer/Counter_c_13" BEL
...@@ -527,10 +483,6 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL ...@@ -527,10 +483,6 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL
"i_Core/i_InterruptManager/int_pointer_r_2" BEL "i_Core/i_InterruptManager/int_pointer_r_2" BEL
"i_Core/i_InterruptManager/int_pointer_r_1" BEL "i_Core/i_InterruptManager/int_pointer_r_1" BEL
"i_Core/i_InterruptManager/int_pointer_r_0" BEL "i_Core/i_InterruptManager/int_pointer_r_0" BEL
"i_Core/i_InterruptManager/int_counter_3" BEL
"i_Core/i_InterruptManager/int_counter_2" BEL
"i_Core/i_InterruptManager/int_counter_1" BEL
"i_Core/i_InterruptManager/int_counter_0" BEL
"i_Core/i_InterruptManager/osc_clk" BEL "i_Core/i_InterruptManager/osc_clk" BEL
"i_Core/i_InterruptManager/mask_reg_7" BEL "i_Core/i_InterruptManager/mask_reg_7" BEL
"i_Core/i_InterruptManager/mask_reg_6" BEL "i_Core/i_InterruptManager/mask_reg_6" BEL
...@@ -551,6 +503,41 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL ...@@ -551,6 +503,41 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL
"i_Core/i_InterruptManager/int_masked_old_0" BEL "i_Core/i_InterruptManager/int_masked_old_0" BEL
"i_Core/i_InterruptManager/Stb_d" BEL "i_Core/i_InterruptManager/Stb_d" BEL
"i_Core/i_InterruptManager/rora_roak" BEL "i_Core/i_InterruptManager/rora_roak" BEL
"i_Core/i_AddressDecoderWB/StbSlv2SerWB_o" BEL
"i_Core/i_AddressDecoderWB/StbSpiMaster_o" BEL
"i_Core/i_AddressDecoderWB/Ack_o" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_31" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_30" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_29" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_28" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_27" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_26" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_25" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_24" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_23" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_22" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_21" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_20" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_19" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_18" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_17" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_16" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_15" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_14" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_13" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_12" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_11" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_10" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_9" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_8" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_7" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_6" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_5" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_4" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_3" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_2" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_1" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_31" BEL "i_Core/i_Generic4OutputRegs/Reg2Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_30" BEL "i_Core/i_Generic4OutputRegs/Reg2Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_29" BEL "i_Core/i_Generic4OutputRegs/Reg2Value_ob32_29" BEL
...@@ -893,9 +880,13 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL ...@@ -893,9 +880,13 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_2" BEL "i_Core/i_SpiMasterWB/Config1_qb32_2" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_1" BEL "i_Core/i_SpiMasterWB/Config1_qb32_1" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_0" BEL "i_Core/i_SpiMasterWB/Config1_qb32_0" BEL
"i_Core/i_VmeInterface/VmeDataDir_oq" BEL
"i_Core/i_VmeInterface/VmeDataOe_oq" BEL
"i_Core/i_InterruptManager/fifo_full" BEL "i_Core/i_InterruptManager/fifo_full" BEL
"i_Core/i_VmeInterface/cyc_o" BEL "i_Core/i_VmeInterface/stb_o" BEL "i_Core/i_VmeInterface/VmeDataRegOe" BEL
"i_Core/i_VmeInterface/vme_iack_outn" BEL "i_Core/i_VmeInterface/Stb_oq" BEL "i_Core/i_VmeInterface/ClearInt_op"
BEL "i_Core/i_VmeInterface/We_oq" BEL
"i_Core/i_VmeInterface/VmeIAckOutn_oqn" BEL
"i_Core/i_SpiMasterWB/SClk_o" BEL "i_Core/i_SpiMasterWB/SS_onb32_1" "i_Core/i_SpiMasterWB/SClk_o" BEL "i_Core/i_SpiMasterWB/SS_onb32_1"
BEL "i_Core/i_SpiMasterWB/SS_onb32_2" BEL BEL "i_Core/i_SpiMasterWB/SS_onb32_2" BEL
"i_Core/i_SpiMasterWB/SS_onb32_0" BEL "i_Core/i_SpiMasterWB/SS_onb32_0" BEL
...@@ -904,15 +895,13 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL ...@@ -904,15 +895,13 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL
"i_Core/i_SpiMasterWB/SS_onb32_3" BEL "i_Core/i_SpiMasterWB/SS_onb32_3" BEL
"i_Core/i_SpiMasterWB/SS_onb32_6" BEL "i_Core/i_SpiMasterWB/SS_onb32_6" BEL
"i_Core/i_SpiMasterWB/SS_onb32_7" BEL "i_Core/i_SpiMasterWB/SS_onb32_7" BEL
"i_Core/i_SpiMasterWB/SS_onb32_8" BEL "i_Core/WriteCycle" BEL "i_Core/i_SpiMasterWB/SS_onb32_8" BEL "i_Core/i_SpiMasterWB/StartTx_q"
"i_Core/i_VmeInterface/state_FSM_FFd1" BEL BEL "i_Core/i_VmeAccessMonostable/SynchOutput_oq" BEL
"i_Core/i_VmeAccessMonostable/SynchOutput_oq" BEL
"i_Core/i_ClearMonostable/SynchOutput_oq" BEL
"i_Core/i_WriteCycleMonostable/SynchOutput_oq" BEL
"i_Core/i_Debouncer/DebouncedSignal_oq" BEL "i_Core/i_Debouncer/DebouncedSignal_oq" BEL
"i_Core/i_AddressDecoderWB/StbGenericOutputRegs_o" BEL
"i_Core/i_AddressDecoderWB/StbIntManager_o" BEL
"i_Core/i_Debouncer/State_q" BEL "i_Core/i_InterruptManager/ready4int" "i_Core/i_Debouncer/State_q" BEL "i_Core/i_InterruptManager/ready4int"
BEL "i_Core/i_InterruptManager/fifo_empty" BEL BEL "i_Core/i_InterruptManager/fifo_empty" BEL
"i_Core/i_SpiMasterWB/StartTx_q" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_31" BEL "i_Core/i_SpiMasterWB/ShiftIn_qb32_31" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_30" BEL "i_Core/i_SpiMasterWB/ShiftIn_qb32_30" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_29" BEL "i_Core/i_SpiMasterWB/ShiftIn_qb32_29" BEL
...@@ -977,28 +966,64 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL ...@@ -977,28 +966,64 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_2" BEL "i_Core/i_SpiMasterWB/ShiftOut_qb32_2" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_1" BEL "i_Core/i_SpiMasterWB/ShiftOut_qb32_1" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_0" BEL "i_Core/i_SpiMasterWB/ShiftOut_qb32_0" BEL
"i_Core/i_VmeInterface/adr_o_3_1" BEL "i_Core/i_InterruptManager/int_counter_3" BEL
"i_Core/i_VmeInterface/adr_o_21_1" BEL "i_Core/i_InterruptManager/int_counter_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_7" BEL "i_Core/i_InterruptManager/int_counter_0" BEL
"i_Core/i_VmeInterface/AckTimeout_c_6" BEL "i_Core/i_InterruptManager/int_counter_2" BEL
"i_Core/i_VmeInterface/AckTimeout_c_8" BEL "i_Core/i_VmeInterface/Adr_obq22_0_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_5" BEL "i_Core/i_VmeInterface/Adr_obq22_2_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_4" BEL "i_Core/i_SpiMasterWB/Config1_qb32_29_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_2" BEL "i_Core/i_SpiMasterWB/State_q_FSM_FFd1_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_1" BEL "i_Core/i_VmeInterface/Adr_obq22_1_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_3" BEL "i_Core/i_SpiMasterWB/State_q_FSM_FFd2_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_0" BEL "VcTcXo_ik_IBUF_BUFG" BEL "i_Core/i_SpiMasterWB/State_q_FSM_FFd3_1" BEL "Si57x_BUFG" BEL
"i_Core/i_ClearMonostable/Mshreg_AsynchInAX_db4_2" BEL "i_Core/i_VmeInterface/VmeDataReg_qb32_31" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_2" BEL "i_Core/i_VmeInterface/VmeDataReg_qb32_30" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_29" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_28" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_27" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_26" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_25" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_24" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_23" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_22" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_21" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_20" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_19" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_18" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_17" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_16" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_15" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_14" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_13" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_12" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_11" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_10" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_9" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_8" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_7" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_6" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_5" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_4" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_3" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_2" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_1" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_0" BEL
"i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL "i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL
"i_Core/i_VmeInterface/Mshreg_Ds1Shr_dq_2" BEL
"i_Core/i_VmeInterface/Ds1Shr_dq_2" BEL
"i_Core/i_VmeInterface/Mshreg_IAckInShr_dq_2" BEL
"i_Core/i_VmeInterface/IAckInShr_dq_2" BEL
"i_Core/i_VmeInterface/Mshreg_AsShr_dq_2" BEL
"i_Core/i_VmeInterface/AsShr_dq_2" BEL
"i_Core/i_VmeInterface/Mshreg_Ds2Shr_dq_2" BEL
"i_Core/i_VmeInterface/Ds2Shr_dq_2" BEL
"i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2" BEL "i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2" BEL "i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL
"i_Core/i_WriteCycleMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_WriteCycleMonostable/AsynchInAX_db4_2" BEL
"i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL "i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL "PllSysRef12_ok" BEL "i_Core/i_Debouncer/BouncingSignal_x_2" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "PllSysRef12_ok" BEL
"PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL "PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL
"PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL "PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL "i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL
...@@ -1013,19 +1038,6 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL ...@@ -1013,19 +1038,6 @@ TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL "i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL "i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD"; "i_Core/i_InterruptManager/Mram_int_fifo1_RAMD";
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
"i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL
"i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL
"i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL
"i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "Si57x_BUFG";
TIMEGRP Si57x_ikn = BEL "i_Core/Si57xDivider_c_23" BEL TIMEGRP Si57x_ikn = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL "i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL "i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
...@@ -1038,20 +1050,698 @@ TIMEGRP Si57x_ikn = BEL "i_Core/Si57xDivider_c_23" BEL ...@@ -1038,20 +1050,698 @@ TIMEGRP Si57x_ikn = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL "i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL "i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL "i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "Si57x_BUFG"; "i_Core/Si57xDivider_c_0" BEL "i_Core/Rst_rq" BEL
TIMEGRP VmeSysClk_ik = BEL "i_Core/VmeSysClkDivider_c_23" BEL "i_Core/i_VmeInterface/State_q_FSM_FFd2" BEL
"i_Core/VmeSysClkDivider_c_22" BEL "i_Core/VmeSysClkDivider_c_21" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_29" BEL
"i_Core/VmeSysClkDivider_c_20" BEL "i_Core/VmeSysClkDivider_c_19" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_28" BEL
"i_Core/VmeSysClkDivider_c_18" BEL "i_Core/VmeSysClkDivider_c_17" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_27" BEL
"i_Core/VmeSysClkDivider_c_16" BEL "i_Core/VmeSysClkDivider_c_15" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_26" BEL
"i_Core/VmeSysClkDivider_c_14" BEL "i_Core/VmeSysClkDivider_c_13" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_25" BEL
"i_Core/VmeSysClkDivider_c_12" BEL "i_Core/VmeSysClkDivider_c_11" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_24" BEL
"i_Core/VmeSysClkDivider_c_10" BEL "i_Core/VmeSysClkDivider_c_9" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_23" BEL
"i_Core/VmeSysClkDivider_c_8" BEL "i_Core/VmeSysClkDivider_c_7" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_22" BEL
"i_Core/VmeSysClkDivider_c_6" BEL "i_Core/VmeSysClkDivider_c_5" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_21" BEL
"i_Core/VmeSysClkDivider_c_4" BEL "i_Core/VmeSysClkDivider_c_3" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_20" BEL
"i_Core/VmeSysClkDivider_c_2" BEL "i_Core/VmeSysClkDivider_c_1" BEL "i_Core/i_VmeInterface/TimoutCounter_cb30_19" BEL
"i_Core/VmeSysClkDivider_c_0" BEL "VmeSysClk_ik_BUFGP/BUFG"; "i_Core/i_VmeInterface/TimoutCounter_cb30_18" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_17" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_16" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_15" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_14" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_13" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_12" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_11" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_10" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_9" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_8" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_7" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_6" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_5" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_4" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_3" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_2" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_1" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_0" BEL
"i_Core/i_VmeInterface/State_q_FSM_FFd1" BEL
"i_Core/i_VmeInterface/Dat_obq32_31" BEL
"i_Core/i_VmeInterface/Dat_obq32_30" BEL
"i_Core/i_VmeInterface/Dat_obq32_29" BEL
"i_Core/i_VmeInterface/Dat_obq32_28" BEL
"i_Core/i_VmeInterface/Dat_obq32_27" BEL
"i_Core/i_VmeInterface/Dat_obq32_26" BEL
"i_Core/i_VmeInterface/Dat_obq32_25" BEL
"i_Core/i_VmeInterface/Dat_obq32_24" BEL
"i_Core/i_VmeInterface/Dat_obq32_23" BEL
"i_Core/i_VmeInterface/Dat_obq32_22" BEL
"i_Core/i_VmeInterface/Dat_obq32_21" BEL
"i_Core/i_VmeInterface/Dat_obq32_20" BEL
"i_Core/i_VmeInterface/Dat_obq32_19" BEL
"i_Core/i_VmeInterface/Dat_obq32_18" BEL
"i_Core/i_VmeInterface/Dat_obq32_17" BEL
"i_Core/i_VmeInterface/Dat_obq32_16" BEL
"i_Core/i_VmeInterface/Dat_obq32_15" BEL
"i_Core/i_VmeInterface/Dat_obq32_14" BEL
"i_Core/i_VmeInterface/Dat_obq32_13" BEL
"i_Core/i_VmeInterface/Dat_obq32_12" BEL
"i_Core/i_VmeInterface/Dat_obq32_11" BEL
"i_Core/i_VmeInterface/Dat_obq32_10" BEL
"i_Core/i_VmeInterface/Dat_obq32_9" BEL
"i_Core/i_VmeInterface/Dat_obq32_8" BEL
"i_Core/i_VmeInterface/Dat_obq32_7" BEL
"i_Core/i_VmeInterface/Dat_obq32_6" BEL
"i_Core/i_VmeInterface/Dat_obq32_5" BEL
"i_Core/i_VmeInterface/Dat_obq32_4" BEL
"i_Core/i_VmeInterface/Dat_obq32_3" BEL
"i_Core/i_VmeInterface/Dat_obq32_2" BEL
"i_Core/i_VmeInterface/Dat_obq32_1" BEL
"i_Core/i_VmeInterface/Dat_obq32_0" BEL
"i_Core/i_VmeInterface/VmeDtAck_oqn" BEL
"i_Core/i_VmeInterface/Adr_obq22_21" BEL
"i_Core/i_VmeInterface/Adr_obq22_20" BEL
"i_Core/i_VmeInterface/Adr_obq22_19" BEL
"i_Core/i_VmeInterface/Adr_obq22_18" BEL
"i_Core/i_VmeInterface/Adr_obq22_17" BEL
"i_Core/i_VmeInterface/Adr_obq22_16" BEL
"i_Core/i_VmeInterface/Adr_obq22_15" BEL
"i_Core/i_VmeInterface/Adr_obq22_14" BEL
"i_Core/i_VmeInterface/Adr_obq22_13" BEL
"i_Core/i_VmeInterface/Adr_obq22_12" BEL
"i_Core/i_VmeInterface/Adr_obq22_11" BEL
"i_Core/i_VmeInterface/Adr_obq22_10" BEL
"i_Core/i_VmeInterface/Adr_obq22_9" BEL
"i_Core/i_VmeInterface/Adr_obq22_8" BEL
"i_Core/i_VmeInterface/Adr_obq22_7" BEL
"i_Core/i_VmeInterface/Adr_obq22_6" BEL
"i_Core/i_VmeInterface/Adr_obq22_5" BEL
"i_Core/i_VmeInterface/Adr_obq22_4" BEL
"i_Core/i_VmeInterface/Adr_obq22_3" BEL
"i_Core/i_VmeInterface/Adr_obq22_2" BEL
"i_Core/i_VmeInterface/Adr_obq22_1" BEL
"i_Core/i_VmeInterface/Adr_obq22_0" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_7" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_6" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_5" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_4" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_3" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_2" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_22" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_20" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_19" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_18" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_17" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_16" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_15" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_14" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_13" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_12" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_11" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_10" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_9" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_8" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_7" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_6" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_5" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_4" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_3" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_2" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_Debouncer/Counter_c_15" BEL
"i_Core/i_Debouncer/Counter_c_14" BEL
"i_Core/i_Debouncer/Counter_c_13" BEL
"i_Core/i_Debouncer/Counter_c_12" BEL
"i_Core/i_Debouncer/Counter_c_11" BEL
"i_Core/i_Debouncer/Counter_c_10" BEL "i_Core/i_Debouncer/Counter_c_9"
BEL "i_Core/i_Debouncer/Counter_c_8" BEL
"i_Core/i_Debouncer/Counter_c_7" BEL "i_Core/i_Debouncer/Counter_c_6"
BEL "i_Core/i_Debouncer/Counter_c_5" BEL
"i_Core/i_Debouncer/Counter_c_4" BEL "i_Core/i_Debouncer/Counter_c_3"
BEL "i_Core/i_Debouncer/Counter_c_2" BEL
"i_Core/i_Debouncer/Counter_c_1" BEL "i_Core/i_Debouncer/Counter_c_0"
BEL "i_Core/i_InterruptManager/int_pointer_w_2" BEL
"i_Core/i_InterruptManager/int_pointer_w_1" BEL
"i_Core/i_InterruptManager/int_pointer_w_0" BEL
"i_Core/i_InterruptManager/int_pointer_r_2" BEL
"i_Core/i_InterruptManager/int_pointer_r_1" BEL
"i_Core/i_InterruptManager/int_pointer_r_0" BEL
"i_Core/i_InterruptManager/osc_clk" BEL
"i_Core/i_InterruptManager/mask_reg_7" BEL
"i_Core/i_InterruptManager/mask_reg_6" BEL
"i_Core/i_InterruptManager/mask_reg_5" BEL
"i_Core/i_InterruptManager/mask_reg_4" BEL
"i_Core/i_InterruptManager/mask_reg_3" BEL
"i_Core/i_InterruptManager/mask_reg_2" BEL
"i_Core/i_InterruptManager/mask_reg_1" BEL
"i_Core/i_InterruptManager/mask_reg_0" BEL
"i_Core/i_InterruptManager/hs_int_mode" BEL
"i_Core/i_InterruptManager/int_masked_old_7" BEL
"i_Core/i_InterruptManager/int_masked_old_6" BEL
"i_Core/i_InterruptManager/int_masked_old_5" BEL
"i_Core/i_InterruptManager/int_masked_old_4" BEL
"i_Core/i_InterruptManager/int_masked_old_3" BEL
"i_Core/i_InterruptManager/int_masked_old_2" BEL
"i_Core/i_InterruptManager/int_masked_old_1" BEL
"i_Core/i_InterruptManager/int_masked_old_0" BEL
"i_Core/i_InterruptManager/Stb_d" BEL
"i_Core/i_InterruptManager/rora_roak" BEL
"i_Core/i_AddressDecoderWB/StbSlv2SerWB_o" BEL
"i_Core/i_AddressDecoderWB/StbSpiMaster_o" BEL
"i_Core/i_AddressDecoderWB/Ack_o" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_31" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_30" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_29" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_28" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_27" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_26" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_25" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_24" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_23" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_22" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_21" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_20" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_19" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_18" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_17" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_16" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_15" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_14" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_13" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_12" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_11" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_10" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_9" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_8" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_7" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_6" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_5" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_4" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_3" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_2" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_1" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_0" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_31" BEL "i_Core/i_Slv2SerWB/Dat_ob32_30"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_29" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_28" BEL "i_Core/i_Slv2SerWB/Dat_ob32_27"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_26" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_25" BEL "i_Core/i_Slv2SerWB/Dat_ob32_24"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_23" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_22" BEL "i_Core/i_Slv2SerWB/Dat_ob32_21"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_20" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_19" BEL "i_Core/i_Slv2SerWB/Dat_ob32_18"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_17" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_16" BEL "i_Core/i_Slv2SerWB/Dat_ob32_15"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_14" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_13" BEL "i_Core/i_Slv2SerWB/Dat_ob32_12"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_11" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_10" BEL "i_Core/i_Slv2SerWB/Dat_ob32_9"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_8" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_7" BEL "i_Core/i_Slv2SerWB/Dat_ob32_6"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_5" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_4" BEL "i_Core/i_Slv2SerWB/Dat_ob32_3"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_2" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_1" BEL "i_Core/i_Slv2SerWB/Dat_ob32_0"
BEL "i_Core/i_Slv2SerWB/Ack_o" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_30" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_29" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_28" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_27" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_26" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_25" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_24" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_23" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_22" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_21" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_20" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_19" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_18" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_17" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_16" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_15" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_14" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_13" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_12" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_11" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_10" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_9" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_8" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_7" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_6" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_5" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_4" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_3" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_2" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_1" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_0" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_30" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_29" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_28" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_27" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_26" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_25" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_24" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_23" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_22" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_21" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_20" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_19" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_18" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_17" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_16" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_15" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_14" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_13" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_12" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_11" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_10" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_9" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_8" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_7" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_6" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_5" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_4" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_3" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_2" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_1" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_0" BEL "i_Core/i_Slv2SerWB/StbI_d"
BEL "i_Core/i_Slv2SerWB/DatOutShReg_b32_31" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_30" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_29" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_28" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_27" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_26" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_25" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_24" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_23" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_22" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_21" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_20" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_19" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_18" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_17" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_16" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_15" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_14" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_13" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_12" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_11" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_10" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_9" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_8" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_7" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_6" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_5" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_4" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_3" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_2" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_1" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_0" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd2" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd3" BEL
"i_Core/i_SpiMasterWB/WriteAck_q" BEL
"i_Core/i_SpiMasterWB/WaitingNewData_o" BEL
"i_Core/i_SpiMasterWB/ModuleIdle_o" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_15" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_14" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_13" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_12" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_11" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_10" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_9" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_8" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_7" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_6" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_5" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_4" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_3" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_2" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_1" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_0" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_11" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_10" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_9" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_8" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_7" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_6" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_5" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_4" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_3" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_2" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_1" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_0" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_31" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_30" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_29" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_28" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_27" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_26" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_25" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_24" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_23" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_22" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_21" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_20" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_19" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_18" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_17" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_16" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_15" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_14" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_13" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_12" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_11" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_10" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_9" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_8" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_7" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_6" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_5" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_4" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_3" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_2" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_1" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_0" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_31" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_30" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_29" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_28" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_27" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_26" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_25" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_24" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_23" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_22" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_21" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_20" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_19" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_18" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_17" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_16" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_15" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_14" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_13" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_12" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_11" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_10" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_9" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_8" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_7" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_6" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_5" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_4" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_3" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_2" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_1" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_0" BEL
"i_Core/i_VmeInterface/VmeDataDir_oq" BEL
"i_Core/i_VmeInterface/VmeDataOe_oq" BEL
"i_Core/i_InterruptManager/fifo_full" BEL
"i_Core/i_VmeInterface/VmeDataRegOe" BEL
"i_Core/i_VmeInterface/Stb_oq" BEL "i_Core/i_VmeInterface/ClearInt_op"
BEL "i_Core/i_VmeInterface/We_oq" BEL
"i_Core/i_VmeInterface/VmeIAckOutn_oqn" BEL
"i_Core/i_SpiMasterWB/SClk_o" BEL "i_Core/i_SpiMasterWB/SS_onb32_1"
BEL "i_Core/i_SpiMasterWB/SS_onb32_2" BEL
"i_Core/i_SpiMasterWB/SS_onb32_0" BEL
"i_Core/i_SpiMasterWB/SS_onb32_4" BEL
"i_Core/i_SpiMasterWB/SS_onb32_5" BEL
"i_Core/i_SpiMasterWB/SS_onb32_3" BEL
"i_Core/i_SpiMasterWB/SS_onb32_6" BEL
"i_Core/i_SpiMasterWB/SS_onb32_7" BEL
"i_Core/i_SpiMasterWB/SS_onb32_8" BEL "i_Core/i_SpiMasterWB/StartTx_q"
BEL "i_Core/i_VmeAccessMonostable/SynchOutput_oq" BEL
"i_Core/i_Debouncer/DebouncedSignal_oq" BEL
"i_Core/i_AddressDecoderWB/StbGenericOutputRegs_o" BEL
"i_Core/i_AddressDecoderWB/StbIntManager_o" BEL
"i_Core/i_Debouncer/State_q" BEL "i_Core/i_InterruptManager/ready4int"
BEL "i_Core/i_InterruptManager/fifo_empty" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_31" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_30" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_29" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_28" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_27" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_26" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_25" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_24" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_23" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_22" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_21" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_20" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_19" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_18" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_17" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_16" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_15" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_14" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_13" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_12" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_11" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_10" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_9" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_8" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_7" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_6" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_5" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_4" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_3" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_2" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_1" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_0" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_31" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_30" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_29" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_28" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_27" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_26" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_25" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_24" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_23" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_22" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_21" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_20" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_19" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_18" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_17" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_16" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_15" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_14" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_13" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_12" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_11" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_10" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_9" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_8" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_7" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_6" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_5" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_4" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_3" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_2" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_1" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_0" BEL
"i_Core/i_InterruptManager/int_counter_3" BEL
"i_Core/i_InterruptManager/int_counter_1" BEL
"i_Core/i_InterruptManager/int_counter_0" BEL
"i_Core/i_InterruptManager/int_counter_2" BEL
"i_Core/i_VmeInterface/Adr_obq22_0_1" BEL
"i_Core/i_VmeInterface/Adr_obq22_2_1" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_29_1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd1_1" BEL
"i_Core/i_VmeInterface/Adr_obq22_1_1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd2_1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd3_1" BEL "Si57x_BUFG" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_31" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_30" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_29" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_28" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_27" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_26" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_25" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_24" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_23" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_22" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_21" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_20" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_19" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_18" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_17" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_16" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_15" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_14" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_13" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_12" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_11" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_10" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_9" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_8" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_7" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_6" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_5" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_4" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_3" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_2" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_1" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_0" BEL
"i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL
"i_Core/i_VmeInterface/Mshreg_Ds1Shr_dq_2" BEL
"i_Core/i_VmeInterface/Ds1Shr_dq_2" BEL
"i_Core/i_VmeInterface/Mshreg_IAckInShr_dq_2" BEL
"i_Core/i_VmeInterface/IAckInShr_dq_2" BEL
"i_Core/i_VmeInterface/Mshreg_AsShr_dq_2" BEL
"i_Core/i_VmeInterface/AsShr_dq_2" BEL
"i_Core/i_VmeInterface/Mshreg_Ds2Shr_dq_2" BEL
"i_Core/i_VmeInterface/Ds2Shr_dq_2" BEL
"i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2" BEL
"i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "PllSysRef12_ok" BEL
"PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL
"PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/SP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo22/DP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo22/SP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMA" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMB_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMB" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD";
TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_30" BEL "i_Core/i_Slv2SerWB/Dat_xb32_29" "i_Core/i_Slv2SerWB/Dat_xb32_30" BEL "i_Core/i_Slv2SerWB/Dat_xb32_29"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_28" BEL BEL "i_Core/i_Slv2SerWB/Dat_xb32_28" BEL
...@@ -1108,10 +1798,8 @@ TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL ...@@ -1108,10 +1798,8 @@ TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_0" BEL "i_Core/i_Slv2SerWB/DatInShReg_b32_0" BEL
"i_Core/i_Slv2SerWB/AckI_d3_2" BEL "i_Core/i_Slv2SerWB/AckI_d3_1" BEL "i_Core/i_Slv2SerWB/AckI_d3_2" BEL "i_Core/i_Slv2SerWB/AckI_d3_1" BEL
"i_Core/i_Slv2SerWB/AckI_d3_0" BEL "SysAppClk_ik_BUFGP/BUFG"; "i_Core/i_Slv2SerWB/AckI_d3_0" BEL "SysAppClk_ik_BUFGP/BUFG";
TS_VcTcXo_ik = PERIOD TIMEGRP "VcTcXo_ik" 25 MHz HIGH 50%; TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
TS_VmeSysClk_ik = PERIOD TIMEGRP "VmeSysClk_ik" 40 MHz HIGH 50%; TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" 120 MHz HIGH 50%;
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 100 MHz HIGH 50%; TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" 100 MHz HIGH 50%;
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 100 MHz HIGH 50%;
SCHEMATIC END; SCHEMATIC END;
trunk/firmware/XilinxISE/SystemFpga/SFpga.prj
View file @ cb70c6e4
verilog work "../../../hdl/design/VmeInterfaceWB.v" verilog work "../../../hdl/design/VmeToWishBone.v"
verilog work "../../../hdl/design/SpiMasterWB.v" verilog work "../../../hdl/design/SpiMasterWB.v"
verilog work "../../../hdl/design/Slv2SerWB.v" verilog work "../../../hdl/design/Slv2SerWB.v"
verilog work "../../../hdl/design/Monostable.v" verilog work "../../../hdl/design/Monostable.v"
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.ptwx
View file @ cb70c6e4
...@@ -329,4 +329,4 @@ ...@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)> <!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)> <!ELEMENT twValue (#PCDATA)>
]> ]>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 100 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="5.091" best="4.909" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.482" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 100 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="7.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 100 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="7.730" best="2.270" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.521" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="7.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_VmeSysClk_ik = PERIOD TIMEGRP &quot;VmeSysClk_ik&quot; 40 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="22.874" best="2.126" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.521" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="22.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_VcTcXo_ik = PERIOD TIMEGRP &quot;VcTcXo_ik&quot; 25 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="27.265" best="12.735" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.413" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport> <twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.331" best="8.002" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.374" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="3.723" best="4.610" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.482" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.syr
View file @ cb70c6e4
...@@ -106,8 +106,8 @@ Slice Utilization Ratio Delta : 5 ...@@ -106,8 +106,8 @@ Slice Utilization Ratio Delta : 5
========================================================================= =========================================================================
* HDL Parsing * * HDL Parsing *
========================================================================= =========================================================================
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/VmeInterfaceWB.v\" into library work Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/VmeToWishBone.v\" into library work
Parsing module <VmeInterfaceWB>. Parsing module <VmeToWishBone>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SpiMasterWB.v\" into library work Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SpiMasterWB.v\" into library work
Parsing module <SpiMasterWB>. Parsing module <SpiMasterWB>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Slv2SerWB.v\" into library work Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Slv2SerWB.v\" into library work
...@@ -129,7 +129,7 @@ Parsing module <AddressDecoderWBSys>. ...@@ -129,7 +129,7 @@ Parsing module <AddressDecoderWBSys>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v\" into library work Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v\" into library work
Parsing module <SystemFpga>. Parsing module <SystemFpga>.
WARNING:HDLCompiler:572 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 250: Macro <dly> is redefined. WARNING:HDLCompiler:572 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 250: Macro <dly> is redefined.
WARNING:HDLCompiler:224 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to input AFpgaProgDone_io WARNING:HDLCompiler:224 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 648: Assignment to input AFpgaProgDone_io
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v\" into library work Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v\" into library work
Parsing module <SFpga>. Parsing module <SFpga>.
...@@ -138,34 +138,38 @@ Parsing module <SFpga>. ...@@ -138,34 +138,38 @@ Parsing module <SFpga>.
========================================================================= =========================================================================
Elaborating module <SFpga>. Elaborating module <SFpga>.
WARNING:HDLCompiler:1016 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 507: Port osc_clk is not connected to this instance WARNING:HDLCompiler:1016 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 546: Port osc_clk is not connected to this instance
Elaborating module <SystemFpga>. Elaborating module <SystemFpga>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 325: Assignment to DdrLDQS_io ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 323: Assignment to DdrLDQS_io ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 326: Assignment to DdrUDQS_io ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 324: Assignment to DdrUDQS_io ignored, since the identifier is never used
Elaborating module <Monostable>. Elaborating module <Monostable>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 370: Assignment to RstForLed ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 381: Assignment to DebugForLed1 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 386: Assignment to DebugForLed2 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 391: Assignment to DebugForLed3 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 396: Assignment to DebugForLed4 ignored, since the identifier is never used
Elaborating module <Debouncer(g_CounterWidth=16,g_SynchDepth=3)>. Elaborating module <Debouncer(g_CounterWidth=16,g_SynchDepth=3)>.
Elaborating module <VmeInterfaceWB>. Elaborating module <VmeToWishBone>.
Elaborating module <InterruptManagerWB>. Elaborating module <InterruptManagerWB>.
Elaborating module <AddressDecoderWBSys>. Elaborating module <AddressDecoderWBSys>.
Elaborating module <Generic4OutputRegs(Reg2Default=32'b01000100010001000)>. Elaborating module <Generic4OutputRegs(Reg2Default=32'b01000100010001000)>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 568: Assignment to GenericOutputReg3 ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to GenericOutputReg3 ignored, since the identifier is never used
Elaborating module <Generic4InputRegs>. Elaborating module <Generic4InputRegs>.
Elaborating module <Slv2SerWB>. Elaborating module <Slv2SerWB>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to AFpgaProgDone_io ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 648: Assignment to AFpgaProgDone_io ignored, since the identifier is never used
Elaborating module <SpiMasterWB>. Elaborating module <SpiMasterWB>.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 268: Net <GenericInputReg1[31]> does not have a driver. WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 268: Net <GenericInputReg1[31]> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 273: Net <SpiMiSo_b32[30]> does not have a driver. WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 273: Net <SpiMiSo_b32[30]> does not have a driver.
WARNING:HDLCompiler:189 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 253: Size mismatch in connection of port <VmeDs_inb2>. Formal port size is 2-bit while actual signal size is 1-bit.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 439: Assignment to WRGBitOut_o ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 439: Assignment to WRGBitOut_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 442: Assignment to Sfp2GBitOut_o ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 442: Assignment to Sfp2GBitOut_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 444: Assignment to SataTx_o ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 444: Assignment to SataTx_o ignored, since the identifier is never used
...@@ -179,7 +183,6 @@ Elaborating module <IBUFGDS(DIFF_TERM="TRUE",IOSTANDARD="DEFAULT")>. ...@@ -179,7 +183,6 @@ Elaborating module <IBUFGDS(DIFF_TERM="TRUE",IOSTANDARD="DEFAULT")>.
Elaborating module <OBUFDS(IOSTANDARD="DEFAULT")>. Elaborating module <OBUFDS(IOSTANDARD="DEFAULT")>.
Elaborating module <IOBUFDS(IOSTANDARD="DEFAULT")>. Elaborating module <IOBUFDS(IOSTANDARD="DEFAULT")>.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 253: Net <VmeDs_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 440: Net <WRGbitIn_i> does not have a driver. WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 440: Net <WRGbitIn_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 441: Net <WRRefClk_ik> does not have a driver. WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 441: Net <WRRefClk_ik> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 443: Net <Sfp2GbitIn_i> does not have a driver. WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 443: Net <Sfp2GbitIn_i> does not have a driver.
...@@ -190,6 +193,11 @@ WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/d ...@@ -190,6 +193,11 @@ WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/d
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 452: Net <Gbit3App2Sys_i> does not have a driver. WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 452: Net <Gbit3App2Sys_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 454: Net <Gbit4App2Sys_i> does not have a driver. WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 454: Net <Gbit4App2Sys_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 455: Net <Gbit34RefClk_ik> does not have a driver. WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 455: Net <Gbit34RefClk_ik> does not have a driver.
WARNING:Xst:2972 - "/vfc_svn/hdl/design/systemfpga.v" line 367. All outputs of instance <i_ClearMonostable> of block <Monostable> are unconnected in block <SystemFpga>. Underlying logic will be removed.
WARNING:Xst:2972 - "/vfc_svn/hdl/design/systemfpga.v" line 378. All outputs of instance <i_Debug1Monostable> of block <Monostable> are unconnected in block <SystemFpga>. Underlying logic will be removed.
WARNING:Xst:2972 - "/vfc_svn/hdl/design/systemfpga.v" line 383. All outputs of instance <i_Debug2Monostable> of block <Monostable> are unconnected in block <SystemFpga>. Underlying logic will be removed.
WARNING:Xst:2972 - "/vfc_svn/hdl/design/systemfpga.v" line 388. All outputs of instance <i_Debug3Monostable> of block <Monostable> are unconnected in block <SystemFpga>. Underlying logic will be removed.
WARNING:Xst:2972 - "/vfc_svn/hdl/design/systemfpga.v" line 393. All outputs of instance <i_Debug4Monostable> of block <Monostable> are unconnected in block <SystemFpga>. Underlying logic will be removed.
========================================================================= =========================================================================
* HDL Synthesis * * HDL Synthesis *
...@@ -197,7 +205,6 @@ WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/d ...@@ -197,7 +205,6 @@ WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/d
Synthesizing Unit <SFpga>. Synthesizing Unit <SFpga>.
Related source file is "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v". Related source file is "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v".
WARNING:Xst:647 - Input <VmeDs_inb2<2:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <WRGBitOut_o> of the instance <i_Core> is unconnected or connected to loadless signal. INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <WRGBitOut_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Sfp2GBitOut_o> of the instance <i_Core> is unconnected or connected to loadless signal. INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Sfp2GBitOut_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <SataTx_o> of the instance <i_Core> is unconnected or connected to loadless signal. INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <SataTx_o> of the instance <i_Core> is unconnected or connected to loadless signal.
...@@ -205,7 +212,6 @@ INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output po ...@@ -205,7 +212,6 @@ INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output po
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit2Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal. INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit2Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit3Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal. INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit3Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit4Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal. INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit4Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <VmeDs_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <WRGbitIn_i> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <WRGbitIn_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <WRRefClk_ik> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <WRRefClk_ik> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Sfp2GbitIn_i> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <Sfp2GbitIn_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
...@@ -224,10 +230,12 @@ Synthesizing Unit <SystemFpga>. ...@@ -224,10 +230,12 @@ Synthesizing Unit <SystemFpga>.
Related source file is "/vfc_svn/hdl/design/systemfpga.v". Related source file is "/vfc_svn/hdl/design/systemfpga.v".
WARNING:Xst:647 - Input <Switch_ib2<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <Switch_ib2<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PcbRev_ib8<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <PcbRev_ib8<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeSysClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTck_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <VmeTck_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTrst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <VmeTrst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTdi_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <VmeTdi_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTms_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <VmeTms_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VcTcXo_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <AFpgaProgDone_io> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <AFpgaProgDone_io> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllFmc12SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <PllFmc12SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllFmc22SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <PllFmc22SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
...@@ -264,8 +272,13 @@ WARNING:Xst:647 - Input <Gbit12RefClk_ik> is never used. This port will be prese ...@@ -264,8 +272,13 @@ WARNING:Xst:647 - Input <Gbit12RefClk_ik> is never used. This port will be prese
WARNING:Xst:647 - Input <Gbit3App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <Gbit3App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit4App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <Gbit4App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit34RefClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <Gbit34RefClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 507: Output port <osc_clk> of the instance <i_InterruptManager> is unconnected or connected to loadless signal. INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 367: Output port <SynchOutput_oq> of the instance <i_ClearMonostable> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 555: Output port <Reg3Value_ob32> of the instance <i_Generic4OutputRegs> is unconnected or connected to loadless signal. INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 378: Output port <SynchOutput_oq> of the instance <i_Debug1Monostable> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 383: Output port <SynchOutput_oq> of the instance <i_Debug2Monostable> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 388: Output port <SynchOutput_oq> of the instance <i_Debug3Monostable> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 393: Output port <SynchOutput_oq> of the instance <i_Debug4Monostable> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 546: Output port <osc_clk> of the instance <i_InterruptManager> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 595: Output port <Reg3Value_ob32> of the instance <i_Generic4OutputRegs> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <GenericInputReg1> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <GenericInputReg1> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <GenericInputReg2> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <GenericInputReg2> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <GenericInputReg3> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <GenericInputReg3> is used but never assigned. This sourceless signal will be automatically connected to value GND.
...@@ -277,50 +290,45 @@ WARNING:Xst:653 - Signal <Gbit1Sys2App_o> is used but never assigned. This sourc ...@@ -277,50 +290,45 @@ WARNING:Xst:653 - Signal <Gbit1Sys2App_o> is used but never assigned. This sourc
WARNING:Xst:653 - Signal <Gbit2Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <Gbit2Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit3Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <Gbit3Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Found 24-bit register for signal <VcTcXoDivider_c>.
Found 24-bit register for signal <VmeSysClkDivider_c>.
Found 1-bit register for signal <WriteCycle>.
Found 2-bit register for signal <VmeSysReset_dx>. Found 2-bit register for signal <VmeSysReset_dx>.
Found 1-bit register for signal <Rst_rq>. Found 1-bit register for signal <Rst_rq>.
Found 24-bit register for signal <Si57xDivider_c>. Found 24-bit register for signal <Si57xDivider_c>.
Found 24-bit adder for signal <Si57xDivider_c[23]_GND_2_o_add_7_OUT> created at line 376. Found 24-bit adder for signal <Si57xDivider_c[23]_GND_2_o_add_7_OUT> created at line 374.
Found 24-bit adder for signal <VcTcXoDivider_c[23]_GND_2_o_add_10_OUT> created at line 379. Found 1-bit tristate buffer for signal <WRModeDef2_io> created at line 294
Found 24-bit adder for signal <VmeSysClkDivider_c[23]_GND_2_o_add_13_OUT> created at line 382. Found 1-bit tristate buffer for signal <Sfp2ModeDef2_io> created at line 298
Found 1-bit tristate buffer for signal <WRModeDef2_io> created at line 296 Found 1-bit tristate buffer for signal <Fmc1SDa_io> created at line 303
Found 1-bit tristate buffer for signal <Sfp2ModeDef2_io> created at line 300 Found 1-bit tristate buffer for signal <Fmc2SDa_io> created at line 305
Found 1-bit tristate buffer for signal <Fmc1SDa_io> created at line 305 Found 1-bit tristate buffer for signal <DdrDQ_iob16<15>> created at line 313
Found 1-bit tristate buffer for signal <Fmc2SDa_io> created at line 307 Found 1-bit tristate buffer for signal <DdrDQ_iob16<14>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<15>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<13>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<14>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<12>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<13>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<11>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<12>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<10>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<11>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<9>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<10>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<8>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<9>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<7>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<8>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<6>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<7>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<5>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<6>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<4>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<5>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<3>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<4>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<2>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<3>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<1>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<2>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<0>> created at line 313
Found 1-bit tristate buffer for signal <DdrDQ_iob16<1>> created at line 315 Found 1-bit tristate buffer for signal <Si57xSDa_io> created at line 336
Found 1-bit tristate buffer for signal <DdrDQ_iob16<0>> created at line 315 Found 1-bit tristate buffer for signal <DdsIOUpdate_io> created at line 345
Found 1-bit tristate buffer for signal <Si57xSDa_io> created at line 338 Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 399
Found 1-bit tristate buffer for signal <DdsIOUpdate_io> created at line 347 Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 400
Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 408 Found 1-bit tristate buffer for signal <FpLed_onb8<2>> created at line 401
Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 409 Found 1-bit tristate buffer for signal <FpLed_onb8<3>> created at line 402
Found 1-bit tristate buffer for signal <FpLed_onb8<2>> created at line 410 Found 1-bit tristate buffer for signal <FpLed_onb8<4>> created at line 411
Found 1-bit tristate buffer for signal <FpLed_onb8<3>> created at line 411 Found 1-bit tristate buffer for signal <FpLed_onb8<5>> created at line 412
Found 1-bit tristate buffer for signal <FpLed_onb8<4>> created at line 412 Found 1-bit tristate buffer for signal <FpLed_onb8<6>> created at line 413
Found 1-bit tristate buffer for signal <FpLed_onb8<5>> created at line 413 Found 1-bit tristate buffer for signal <FpLed_onb8<7>> created at line 414
Found 1-bit tristate buffer for signal <FpLed_onb8<6>> created at line 414 Found 1-bit tristate buffer for signal <AFpgaProgProgram_o> created at line 649
Found 1-bit tristate buffer for signal <FpLed_onb8<7>> created at line 418 Found 1-bit tristate buffer for signal <VAdjInhibit_ozn> created at line 696
Found 1-bit tristate buffer for signal <AFpgaProgProgram_o> created at line 609
Found 1-bit tristate buffer for signal <VAdjInhibit_ozn> created at line 656
Summary: Summary:
inferred 3 Adder/Subtractor(s). inferred 1 Adder/Subtractor(s).
inferred 76 D-type flip-flop(s). inferred 27 D-type flip-flop(s).
inferred 32 Tristate(s). inferred 32 Tristate(s).
Unit <SystemFpga> synthesized. Unit <SystemFpga> synthesized.
...@@ -353,94 +361,84 @@ Synthesizing Unit <Debouncer>. ...@@ -353,94 +361,84 @@ Synthesizing Unit <Debouncer>.
inferred 1 Comparator(s). inferred 1 Comparator(s).
Unit <Debouncer> synthesized. Unit <Debouncer> synthesized.
Synthesizing Unit <VmeInterfaceWB>. Synthesizing Unit <VmeToWishBone>.
Related source file is "/vfc_svn/hdl/design/vmeinterfacewb.v". Related source file is "/vfc_svn/hdl/design/vmetowishbone.v".
dly = 1 Found 3-bit register for signal <Ds2Shr_dq>.
s_idle = 3'b000 Found 3-bit register for signal <AsShr_dq>.
s_read = 3'b001 Found 3-bit register for signal <IAckInShr_dq>.
s_write = 3'b010 Found 7-bit register for signal <VmeIrqn_oqnb7>.
s_ack_int = 3'b011 Found 2-bit register for signal <State_q>.
Found 1-bit register for signal <ack_d>. Found 22-bit register for signal <Adr_obq22>.
Found 1-bit register for signal <stb_d>. Found 32-bit register for signal <Dat_obq32>.
Found 9-bit register for signal <AckTimeout_c>. Found 1-bit register for signal <We_oq>.
Found 32-bit register for signal <DataReg>. Found 1-bit register for signal <Stb_oq>.
Found 2-bit register for signal <as_shr>. Found 1-bit register for signal <Cyc_oq>.
Found 2-bit register for signal <ds1_shr>. Found 1-bit register for signal <VmeDtAck_oqn>.
Found 2-bit register for signal <ds2_shr>. Found 32-bit register for signal <VmeDataReg_qb32>.
Found 7-bit register for signal <vme_irqn>. Found 1-bit register for signal <VmeDataRegOe>.
Found 3-bit register for signal <state>. Found 1-bit register for signal <VmeDataOe_oq>.
Found 1-bit register for signal <oe_vme_data>. Found 1-bit register for signal <VmeDataDir_oq>.
Found 1-bit register for signal <vme_dtack>. Found 1-bit register for signal <ClearInt_op>.
Found 1-bit register for signal <vme_iack_outn>. Found 1-bit register for signal <VmeIAckOutn_oqn>.
Found 1-bit register for signal <clear_int>. Found 30-bit register for signal <TimoutCounter_cb30>.
Found 1-bit register for signal <VmeDOe_o>. Found 3-bit register for signal <Ds1Shr_dq>.
Found 1-bit register for signal <VmeDDirFpgaToVme_o>. Found finite state machine <FSM_0> for signal <State_q>.
Found 1-bit register for signal <SendIrqVector>.
Found 22-bit register for signal <adr_o>.
Found 32-bit register for signal <dat_o>.
Found 1-bit register for signal <we_o>.
Found 1-bit register for signal <stb_o>.
Found 1-bit register for signal <cyc_o>.
Found 8-bit register for signal <VmeBaseAddr>.
Found finite state machine <FSM_0> for signal <state>.
----------------------------------------------------------------------- -----------------------------------------------------------------------
| States | 4 | | States | 4 |
| Transitions | 50 | | Transitions | 19 |
| Inputs | 12 | | Inputs | 14 |
| Outputs | 6 | | Outputs | 10 |
| Clock | clk_i (rising_edge) | | Clock | Clk_ik (rising_edge) |
| Reset | rst_i (positive) | | Reset | Rst_irq (positive) |
| Reset type | synchronous | | Reset type | synchronous |
| Reset State | 000 | | Reset State | 00 |
| Encoding | auto | | Encoding | auto |
| Implementation | LUT | | Implementation | LUT |
----------------------------------------------------------------------- -----------------------------------------------------------------------
Found 9-bit adder for signal <AckTimeout_c[8]_GND_35_o_add_16_OUT> created at line 100. Found 30-bit adder for signal <TimoutCounter_cb30[29]_GND_35_o_add_49_OUT> created at line 184.
Found 22-bit adder for signal <adr_o[21]_GND_35_o_add_48_OUT> created at line 200. Found 1-bit 4-to-1 multiplexer for signal <State_q[1]_VmeDataRegOe_Mux_54_o> created at line 126.
Found 1-bit 4-to-1 multiplexer for signal <_n0284> created at line 148. Found 1-bit tristate buffer for signal <VmeData_iozb32<31>> created at line 109
Found 1-bit 4-to-1 multiplexer for signal <_n0316> created at line 148. Found 1-bit tristate buffer for signal <VmeData_iozb32<30>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<31>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<29>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<30>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<28>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<29>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<27>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<28>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<26>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<27>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<25>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<26>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<24>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<25>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<23>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<24>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<22>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<23>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<21>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<22>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<20>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<21>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<19>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<20>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<18>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<19>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<17>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<18>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<16>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<17>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<15>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<16>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<14>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<15>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<13>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<14>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<12>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<13>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<11>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<12>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<10>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<11>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<9>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<10>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<8>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<9>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<7>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<8>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<6>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<7>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<5>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<6>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<4>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<5>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<3>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<4>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<2>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<3>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<1>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<2>> created at line 110 Found 1-bit tristate buffer for signal <VmeData_iozb32<0>> created at line 109
Found 1-bit tristate buffer for signal <vme_data<1>> created at line 110 Found 8-bit comparator equal for signal <ValidRWBA_a> created at line 62
Found 1-bit tristate buffer for signal <vme_data<0>> created at line 110 Found 3-bit comparator equal for signal <ValidIntAckBA_a> created at line 63
Found 8-bit comparator equal for signal <VmeBaseAddr[7]_GND_35_o_equal_12_o> created at line 75
Found 3-bit comparator equal for signal <vme_addr[3]_intlev_reg[2]_equal_43_o> created at line 178
Summary: Summary:
inferred 2 Adder/Subtractor(s). inferred 1 Adder/Subtractor(s).
inferred 128 D-type flip-flop(s). inferred 144 D-type flip-flop(s).
inferred 2 Comparator(s). inferred 2 Comparator(s).
inferred 28 Multiplexer(s). inferred 21 Multiplexer(s).
inferred 32 Tristate(s). inferred 32 Tristate(s).
inferred 1 Finite State Machine(s). inferred 1 Finite State Machine(s).
Unit <VmeInterfaceWB> synthesized. Unit <VmeToWishBone> synthesized.
Synthesizing Unit <InterruptManagerWB>. Synthesizing Unit <InterruptManagerWB>.
Related source file is "/vfc_svn/hdl/design/interruptmanagerwb.v". Related source file is "/vfc_svn/hdl/design/interruptmanagerwb.v".
...@@ -483,9 +481,17 @@ Synthesizing Unit <AddressDecoderWBSys>. ...@@ -483,9 +481,17 @@ Synthesizing Unit <AddressDecoderWBSys>.
Related source file is "/vfc_svn/hdl/design/addrdecoderwbsys.v". Related source file is "/vfc_svn/hdl/design/addrdecoderwbsys.v".
WARNING:Xst:647 - Input <Adr_ib22<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <Adr_ib22<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <AckGenericInputRegs_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <AckGenericInputRegs_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 32-bit 4-to-1 multiplexer for signal <_n0045> created at line 4. Found 32-bit register for signal <Dat_ob32>.
Found 1-bit register for signal <StbIntManager_o>.
Found 1-bit register for signal <StbGenericOutputRegs_o>.
Found 1-bit register for signal <StbGenericInputRegs_o>.
Found 1-bit register for signal <StbSlv2SerWB_o>.
Found 1-bit register for signal <StbSpiMaster_o>.
Found 1-bit register for signal <Ack_o>.
Found 32-bit 4-to-1 multiplexer for signal <_n0053> created at line 41.
Summary: Summary:
inferred 14 Multiplexer(s). inferred 38 D-type flip-flop(s).
inferred 11 Multiplexer(s).
Unit <AddressDecoderWBSys> synthesized. Unit <AddressDecoderWBSys> synthesized.
Synthesizing Unit <Generic4OutputRegs>. Synthesizing Unit <Generic4OutputRegs>.
...@@ -610,54 +616,52 @@ HDL Synthesis Report ...@@ -610,54 +616,52 @@ HDL Synthesis Report
Macro Statistics Macro Statistics
# RAMs : 1 # RAMs : 1
8x8-bit dual-port RAM : 1 8x8-bit dual-port RAM : 1
# Adders/Subtractors : 14 # Adders/Subtractors : 9
12-bit adder : 1 12-bit adder : 1
16-bit adder : 2 16-bit adder : 2
22-bit adder : 1 23-bit adder : 1
23-bit adder : 3 24-bit adder : 1
24-bit adder : 3
3-bit adder : 2 3-bit adder : 2
30-bit adder : 1
4-bit addsub : 1 4-bit addsub : 1
9-bit adder : 1 # Registers : 107
# Registers : 114 1-bit register : 69
1-bit register : 71
12-bit register : 1 12-bit register : 1
16-bit register : 2 16-bit register : 2
2-bit register : 4 2-bit register : 1
22-bit register : 1 22-bit register : 1
23-bit register : 3 23-bit register : 1
24-bit register : 3 24-bit register : 1
3-bit register : 4 3-bit register : 8
30-bit register : 1
31-bit register : 1 31-bit register : 1
32-bit register : 15 32-bit register : 16
4-bit register : 4 4-bit register : 2
7-bit register : 1 7-bit register : 1
8-bit register : 3 8-bit register : 2
9-bit register : 1
# Comparators : 9 # Comparators : 9
1-bit comparator equal : 1 1-bit comparator equal : 1
12-bit comparator equal : 1 12-bit comparator equal : 1
16-bit comparator equal : 2 16-bit comparator equal : 2
3-bit comparator equal : 4 3-bit comparator equal : 4
8-bit comparator equal : 1 8-bit comparator equal : 1
# Multiplexers : 86 # Multiplexers : 76
1-bit 2-to-1 multiplexer : 44 1-bit 2-to-1 multiplexer : 34
1-bit 32-to-1 multiplexer : 1 1-bit 32-to-1 multiplexer : 1
1-bit 4-to-1 multiplexer : 2 1-bit 4-to-1 multiplexer : 1
12-bit 2-to-1 multiplexer : 2 12-bit 2-to-1 multiplexer : 2
16-bit 2-to-1 multiplexer : 8 16-bit 2-to-1 multiplexer : 8
22-bit 2-to-1 multiplexer : 2 22-bit 2-to-1 multiplexer : 3
32-bit 2-to-1 multiplexer : 20 30-bit 2-to-1 multiplexer : 1
32-bit 2-to-1 multiplexer : 21
32-bit 4-to-1 multiplexer : 3 32-bit 4-to-1 multiplexer : 3
32-bit 7-to-1 multiplexer : 1 32-bit 7-to-1 multiplexer : 1
5-bit 2-to-1 multiplexer : 1 5-bit 2-to-1 multiplexer : 1
7-bit 2-to-1 multiplexer : 1
9-bit 2-to-1 multiplexer : 1
# Tristates : 64 # Tristates : 64
1-bit tristate buffer : 64 1-bit tristate buffer : 64
# FSMs : 2 # FSMs : 2
# Xors : 5 # Xors : 3
1-bit xor2 : 3 1-bit xor2 : 1
1-bit xor6 : 2 1-bit xor6 : 2
========================================================================= =========================================================================
...@@ -666,10 +670,6 @@ Macro Statistics ...@@ -666,10 +670,6 @@ Macro Statistics
* Advanced HDL Synthesis * * Advanced HDL Synthesis *
========================================================================= =========================================================================
WARNING:Xst:1710 - FF/Latch <ds1_shr_0> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ds2_shr_0> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds1_shr_1> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds2_shr_1> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.
Synthesizing (advanced) Unit <Debouncer>. Synthesizing (advanced) Unit <Debouncer>.
The following registers are absorbed into counter <Counter_c>: 1 register on signal <Counter_c>. The following registers are absorbed into counter <Counter_c>: 1 register on signal <Counter_c>.
...@@ -702,14 +702,12 @@ The following registers are absorbed into counter <Counter_c>: 1 register on sig ...@@ -702,14 +702,12 @@ The following registers are absorbed into counter <Counter_c>: 1 register on sig
Unit <Monostable> synthesized (advanced). Unit <Monostable> synthesized (advanced).
Synthesizing (advanced) Unit <SystemFpga>. Synthesizing (advanced) Unit <SystemFpga>.
The following registers are absorbed into counter <VmeSysClkDivider_c>: 1 register on signal <VmeSysClkDivider_c>.
The following registers are absorbed into counter <Si57xDivider_c>: 1 register on signal <Si57xDivider_c>. The following registers are absorbed into counter <Si57xDivider_c>: 1 register on signal <Si57xDivider_c>.
The following registers are absorbed into counter <VcTcXoDivider_c>: 1 register on signal <VcTcXoDivider_c>.
Unit <SystemFpga> synthesized (advanced). Unit <SystemFpga> synthesized (advanced).
Synthesizing (advanced) Unit <VmeInterfaceWB>. Synthesizing (advanced) Unit <VmeToWishBone>.
The following registers are absorbed into counter <AckTimeout_c>: 1 register on signal <AckTimeout_c>. The following registers are absorbed into counter <TimoutCounter_cb30>: 1 register on signal <TimoutCounter_cb30>.
Unit <VmeInterfaceWB> synthesized (advanced). Unit <VmeToWishBone> synthesized (advanced).
========================================================================= =========================================================================
Advanced HDL Synthesis Report Advanced HDL Synthesis Report
...@@ -717,41 +715,39 @@ Advanced HDL Synthesis Report ...@@ -717,41 +715,39 @@ Advanced HDL Synthesis Report
Macro Statistics Macro Statistics
# RAMs : 1 # RAMs : 1
8x8-bit dual-port distributed RAM : 1 8x8-bit dual-port distributed RAM : 1
# Adders/Subtractors : 5 # Adders/Subtractors : 4
12-bit adder : 1 12-bit adder : 1
16-bit adder : 1 16-bit adder : 1
22-bit adder : 1
3-bit adder : 2 3-bit adder : 2
# Counters : 11 # Counters : 7
16-bit up counter : 1 16-bit up counter : 1
23-bit up counter : 3 23-bit up counter : 1
24-bit up counter : 3 24-bit up counter : 1
3-bit up counter : 2 3-bit up counter : 2
30-bit up counter : 1
4-bit updown counter : 1 4-bit updown counter : 1
9-bit up counter : 1 # Registers : 709
# Registers : 689 Flip-Flops : 709
Flip-Flops : 689
# Comparators : 9 # Comparators : 9
1-bit comparator equal : 1 1-bit comparator equal : 1
12-bit comparator equal : 1 12-bit comparator equal : 1
16-bit comparator equal : 2 16-bit comparator equal : 2
3-bit comparator equal : 4 3-bit comparator equal : 4
8-bit comparator equal : 1 8-bit comparator equal : 1
# Multiplexers : 116 # Multiplexers : 106
1-bit 2-to-1 multiplexer : 44 1-bit 2-to-1 multiplexer : 34
1-bit 32-to-1 multiplexer : 1 1-bit 32-to-1 multiplexer : 1
1-bit 4-to-1 multiplexer : 34 1-bit 4-to-1 multiplexer : 33
12-bit 2-to-1 multiplexer : 2 12-bit 2-to-1 multiplexer : 2
16-bit 2-to-1 multiplexer : 8 16-bit 2-to-1 multiplexer : 8
22-bit 2-to-1 multiplexer : 2 22-bit 2-to-1 multiplexer : 3
32-bit 2-to-1 multiplexer : 20 32-bit 2-to-1 multiplexer : 21
32-bit 4-to-1 multiplexer : 2 32-bit 4-to-1 multiplexer : 2
32-bit 7-to-1 multiplexer : 1 32-bit 7-to-1 multiplexer : 1
5-bit 2-to-1 multiplexer : 1 5-bit 2-to-1 multiplexer : 1
7-bit 2-to-1 multiplexer : 1
# FSMs : 2 # FSMs : 2
# Xors : 5 # Xors : 3
1-bit xor2 : 3 1-bit xor2 : 1
1-bit xor6 : 2 1-bit xor6 : 2
========================================================================= =========================================================================
...@@ -759,19 +755,15 @@ Macro Statistics ...@@ -759,19 +755,15 @@ Macro Statistics
========================================================================= =========================================================================
* Low Level Synthesis * * Low Level Synthesis *
========================================================================= =========================================================================
INFO:Xst:2261 - The FF/Latch <ds1_shr_0> in Unit <VmeInterfaceWB> is equivalent to the following FF/Latch, which will be removed : <ds2_shr_0>
WARNING:Xst:1710 - FF/Latch <ds1_shr_0> (without init value) has a constant value of 0 in block <VmeInterfaceWB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds1_shr_1> (without init value) has a constant value of 0 in block <VmeInterfaceWB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds2_shr_1> (without init value) has a constant value of 0 in block <VmeInterfaceWB>. This FF/Latch will be trimmed during the optimization process.
Analyzing FSM <MFsm> for best encoding. Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <i_Core/i_VmeInterface/FSM_0> on signal <state[1:2]> with sequential encoding. Optimizing FSM <i_Core/i_VmeInterface/FSM_0> on signal <State_q[1:2]> with sequential encoding.
------------------- -------------------
State | Encoding State | Encoding
------------------- -------------------
000 | 00 00 | 00
011 | 01 11 | 01
010 | 10 01 | 10
001 | 11 10 | 11
------------------- -------------------
Analyzing FSM <MFsm> for best encoding. Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <i_Core/i_SpiMasterWB/FSM_1> on signal <State_q[1:3]> with user encoding. Optimizing FSM <i_Core/i_SpiMasterWB/FSM_1> on signal <State_q[1:3]> with user encoding.
...@@ -786,6 +778,7 @@ Optimizing FSM <i_Core/i_SpiMasterWB/FSM_1> on signal <State_q[1:3]> with user e ...@@ -786,6 +778,7 @@ Optimizing FSM <i_Core/i_SpiMasterWB/FSM_1> on signal <State_q[1:3]> with user e
101 | 101 101 | 101
------------------- -------------------
WARNING:Xst:1293 - FF/Latch <CntrlShReg_b32_31> has a constant value of 0 in block <Slv2SerWB>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <CntrlShReg_b32_31> has a constant value of 0 in block <Slv2SerWB>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <Stb_oq> in Unit <VmeToWishBone> is equivalent to the following FF/Latch, which will be removed : <Cyc_oq>
Optimizing unit <SFpga> ... Optimizing unit <SFpga> ...
...@@ -795,13 +788,14 @@ Optimizing unit <Debouncer> ... ...@@ -795,13 +788,14 @@ Optimizing unit <Debouncer> ...
Optimizing unit <InterruptManagerWB> ... Optimizing unit <InterruptManagerWB> ...
Optimizing unit <AddressDecoderWBSys> ...
Optimizing unit <Generic4OutputRegs> ... Optimizing unit <Generic4OutputRegs> ...
Optimizing unit <Slv2SerWB> ... Optimizing unit <Slv2SerWB> ...
Optimizing unit <SpiMasterWB> ... Optimizing unit <SpiMasterWB> ...
WARNING:Xst:2677 - Node <i_Core/i_AddressDecoderWB/StbGenericInputRegs_o> of sequential type is unconnected in block <SFpga>.
Optimizing unit <AddressDecoderWBSys> ...
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_9> of sequential type is unconnected in block <SFpga>. WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_9> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_10> of sequential type is unconnected in block <SFpga>. WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_10> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_11> of sequential type is unconnected in block <SFpga>. WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_11> of sequential type is unconnected in block <SFpga>.
...@@ -829,16 +823,23 @@ WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_29> of sequential type is ...@@ -829,16 +823,23 @@ WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_29> of sequential type is
Mapping all equations... Mapping all equations...
Building and optimizing final netlist ... Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SFpga, actual ratio is 1. Found area constraint ratio of 100 (+ 5) on block SFpga, actual ratio is 1.
FlipFlop i_Core/i_VmeInterface/adr_o_21 has been replicated 1 time(s) FlipFlop i_Core/i_SpiMasterWB/Config1_qb32_29 has been replicated 1 time(s)
FlipFlop i_Core/i_VmeInterface/adr_o_3 has been replicated 1 time(s) FlipFlop i_Core/i_SpiMasterWB/State_q_FSM_FFd1 has been replicated 1 time(s)
FlipFlop i_Core/i_SpiMasterWB/State_q_FSM_FFd2 has been replicated 1 time(s)
FlipFlop i_Core/i_SpiMasterWB/State_q_FSM_FFd3 has been replicated 1 time(s)
FlipFlop i_Core/i_VmeInterface/Adr_obq22_0 has been replicated 1 time(s)
FlipFlop i_Core/i_VmeInterface/Adr_obq22_1 has been replicated 1 time(s)
FlipFlop i_Core/i_VmeInterface/Adr_obq22_2 has been replicated 1 time(s)
Final Macro Processing ... Final Macro Processing ...
Processing Unit <SFpga> : Processing Unit <SFpga> :
Found 2-bit shift register for signal <i_Core/VmeSysReset_dx_1>. Found 2-bit shift register for signal <i_Core/VmeSysReset_dx_1>.
Found 3-bit shift register for signal <i_Core/i_VmeInterface/Ds1Shr_dq_2>.
Found 3-bit shift register for signal <i_Core/i_VmeInterface/IAckInShr_dq_2>.
Found 3-bit shift register for signal <i_Core/i_VmeInterface/AsShr_dq_2>.
Found 3-bit shift register for signal <i_Core/i_VmeInterface/Ds2Shr_dq_2>.
Found 3-bit shift register for signal <i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2>. Found 3-bit shift register for signal <i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2>.
Found 3-bit shift register for signal <i_Core/i_ClearMonostable/AsynchInAX_db4_2>.
Found 3-bit shift register for signal <i_Core/i_WriteCycleMonostable/AsynchInAX_db4_2>.
Found 3-bit shift register for signal <i_Core/i_Debouncer/BouncingSignal_x_2>. Found 3-bit shift register for signal <i_Core/i_Debouncer/BouncingSignal_x_2>.
Found 2-bit shift register for signal <i_Core/i_Slv2SerWB/AckI_xb3_0>. Found 2-bit shift register for signal <i_Core/i_Slv2SerWB/AckI_xb3_0>.
Unit <SFpga> processed. Unit <SFpga> processed.
...@@ -847,11 +848,11 @@ Unit <SFpga> processed. ...@@ -847,11 +848,11 @@ Unit <SFpga> processed.
Final Register Report Final Register Report
Macro Statistics Macro Statistics
# Registers : 828 # Registers : 776
Flip-Flops : 828 Flip-Flops : 776
# Shift Registers : 6 # Shift Registers : 8
2-bit shift register : 2 2-bit shift register : 2
3-bit shift register : 4 3-bit shift register : 6
========================================================================= =========================================================================
...@@ -874,43 +875,43 @@ Top Level Output File Name : SFpga.ngc ...@@ -874,43 +875,43 @@ Top Level Output File Name : SFpga.ngc
Primitive and Black Box Usage: Primitive and Black Box Usage:
------------------------------ ------------------------------
# BELS : 1555 # BELS : 1236
# GND : 1 # GND : 1
# INV : 32 # INV : 23
# LUT1 : 197 # LUT1 : 86
# LUT2 : 168 # LUT2 : 211
# LUT3 : 130 # LUT3 : 149
# LUT4 : 116 # LUT4 : 85
# LUT5 : 148 # LUT5 : 123
# LUT6 : 298 # LUT6 : 284
# MUXCY : 220 # MUXCY : 128
# MUXF7 : 28 # MUXF7 : 24
# VCC : 1 # VCC : 1
# XORCY : 216 # XORCY : 121
# FlipFlops/Latches : 834 # FlipFlops/Latches : 784
# FD : 195 # FD : 165
# FDE : 102 # FDE : 104
# FDPE : 1 # FDPE : 1
# FDR : 135 # FDR : 170
# FDRE : 342 # FDRE : 310
# FDS : 26 # FDS : 26
# FDSE : 33 # FDSE : 8
# RAMS : 3 # RAMS : 3
# RAM16X1D : 2 # RAM16X1D : 2
# RAM32M : 1 # RAM32M : 1
# Shift Registers : 6 # Shift Registers : 8
# SRLC16E : 6 # SRLC16E : 8
# Clock Buffers : 4 # Clock Buffers : 2
# BUFG : 2 # BUFG : 1
# BUFGP : 2 # BUFGP : 1
# IO Buffers : 303 # IO Buffers : 304
# IBUF : 76 # IBUF : 77
# IBUFGDS : 6 # IBUFGDS : 6
# IOBUF : 32 # IOBUF : 32
# IOBUFDS : 2 # IOBUFDS : 2
# OBUF : 152 # OBUF : 154
# OBUFDS : 3 # OBUFDS : 3
# OBUFT : 32 # OBUFT : 30
Device utilization summary: Device utilization summary:
--------------------------- ---------------------------
...@@ -919,26 +920,26 @@ Selected Device : 6slx150tfgg676-3 ...@@ -919,26 +920,26 @@ Selected Device : 6slx150tfgg676-3
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 834 out of 184304 0% Number of Slice Registers: 784 out of 184304 0%
Number of Slice LUTs: 1103 out of 92152 1% Number of Slice LUTs: 977 out of 92152 1%
Number used as Logic: 1089 out of 92152 1% Number used as Logic: 961 out of 92152 1%
Number used as Memory: 14 out of 21680 0% Number used as Memory: 16 out of 21680 0%
Number used as RAM: 8 Number used as RAM: 8
Number used as SRL: 6 Number used as SRL: 8
Slice Logic Distribution: Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1319 Number of LUT Flip Flop pairs used: 1207
Number with an unused Flip Flop: 485 out of 1319 36% Number with an unused Flip Flop: 423 out of 1207 35%
Number with an unused LUT: 216 out of 1319 16% Number with an unused LUT: 230 out of 1207 19%
Number of fully used LUT-FF pairs: 618 out of 1319 46% Number of fully used LUT-FF pairs: 554 out of 1207 45%
Number of unique control sets: 34 Number of unique control sets: 25
IO Utilization: IO Utilization:
Number of IOs: 365 Number of IOs: 365
Number of bonded IOBs: 316 out of 396 79% Number of bonded IOBs: 316 out of 396 79%
Specific Feature Utilization: Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 4 out of 16 25% Number of BUFG/BUFGCTRLs: 2 out of 16 12%
--------------------------- ---------------------------
Partition Resource Summary: Partition Resource Summary:
...@@ -958,17 +959,13 @@ NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. ...@@ -958,17 +959,13 @@ NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
Clock Information: Clock Information:
------------------ ------------------
-----------------------------------+------------------------------------------------+-------+ -----------------------------------+-----------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load | Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------------------------------+-------+ -----------------------------------+-----------------------------------------------+-------+
VcTcXo_ik | IBUF+BUFG | 724 | Si57x_ik | IBUFGDS+BUFG | 726 |
Si57x_ik | IBUFGDS+BUFG | 24 | i_Core/i_VmeInterface/Stb_oq | NONE(i_Core/i_VmeAccessMonostable/AsynchIn_ax)| 1 |
VmeSysClk_ik | BUFGP | 24 | SysAppClk_ik | BUFGP | 68 |
i_Core/i_VmeInterface/stb_o | NONE(i_Core/i_VmeAccessMonostable/AsynchIn_ax) | 1 | -----------------------------------+-----------------------------------------------+-------+
i_Core/Rst_rq | NONE(i_Core/i_ClearMonostable/AsynchIn_ax) | 1 |
i_Core/WriteCycle | NONE(i_Core/i_WriteCycleMonostable/AsynchIn_ax)| 1 |
SysAppClk_ik | BUFGP | 68 |
-----------------------------------+------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information: Asynchronous Control Signals Information:
...@@ -979,143 +976,56 @@ Timing Summary: ...@@ -979,143 +976,56 @@ Timing Summary:
--------------- ---------------
Speed Grade: -3 Speed Grade: -3
Minimum period: 8.328ns (Maximum Frequency: 120.083MHz) Minimum period: 6.551ns (Maximum Frequency: 152.654MHz)
Minimum input arrival time before clock: 8.362ns Minimum input arrival time before clock: 12.165ns
Maximum output required time after clock: 6.030ns Maximum output required time after clock: 6.177ns
Maximum combinational path delay: 6.896ns Maximum combinational path delay: 6.926ns
Timing Details: Timing Details:
--------------- ---------------
All values displayed in nanoseconds (ns) All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Clock period: 8.328ns (frequency: 120.083MHz)
Total number of paths / destination ports: 45868 / 1672
-------------------------------------------------------------------------
Delay: 8.328ns (Levels of Logic = 5)
Source: i_Core/i_VmeInterface/adr_o_21_1 (FF)
Destination: i_Core/i_VmeInterface/DataReg_31 (FF)
Source Clock: VcTcXo_ik rising
Destination Clock: VcTcXo_ik rising
Data Path: i_Core/i_VmeInterface/adr_o_21_1 to i_Core/i_VmeInterface/DataReg_31
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 2 0.525 1.047 i_Core/i_VmeInterface/adr_o_21_1 (i_Core/i_VmeInterface/adr_o_21_1)
LUT6:I1->O 4 0.254 0.912 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o13 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12)
LUT4:I1->O 1 0.235 0.688 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1)
LUT5:I3->O 5 0.250 0.715 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 (i_Core/StbSpiMaster)
LUT6:I5->O 58 0.254 1.601 i_Core/i_AddressDecoderWB/Ack_o (i_Core/AckMaster)
LUT3:I2->O 32 0.254 1.291 i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_33_o2 (i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_33_o)
FDSE:CE 0.302 i_Core/i_VmeInterface/DataReg_0
----------------------------------------
Total 8.328ns (2.074ns logic, 6.254ns route)
(24.9% logic, 75.1% route)
========================================================================= =========================================================================
Timing constraint: Default period analysis for Clock 'Si57x_ik' Timing constraint: Default period analysis for Clock 'Si57x_ik'
Clock period: 2.365ns (frequency: 422.770MHz) Clock period: 6.551ns (frequency: 152.654MHz)
Total number of paths / destination ports: 300 / 24 Total number of paths / destination ports: 30716 / 1604
------------------------------------------------------------------------- -------------------------------------------------------------------------
Delay: 2.365ns (Levels of Logic = 25) Delay: 6.551ns (Levels of Logic = 10)
Source: i_Core/Si57xDivider_c_0 (FF) Source: i_Core/i_SpiMasterWB/Config2_qb32_2 (FF)
Destination: i_Core/Si57xDivider_c_23 (FF) Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_31 (FF)
Source Clock: Si57x_ik rising Source Clock: Si57x_ik rising
Destination Clock: Si57x_ik rising Destination Clock: Si57x_ik rising
Data Path: i_Core/Si57xDivider_c_0 to i_Core/Si57xDivider_c_23 Data Path: i_Core/i_SpiMasterWB/Config2_qb32_2 to i_Core/i_SpiMasterWB/ShiftIn_qb32_31
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
FD:C->Q 1 0.525 0.579 i_Core/Si57xDivider_c_0 (i_Core/Si57xDivider_c_0) FDRE:C->Q 2 0.525 1.072 i_Core/i_SpiMasterWB/Config2_qb32_2 (i_Core/i_SpiMasterWB/Config2_qb32_2)
INV:I->O 1 0.255 0.000 i_Core/Mcount_Si57xDivider_c_lut<0>_INV_0 (i_Core/Mcount_Si57xDivider_c_lut<0>) LUT6:I0->O 1 0.254 0.000 i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_lut<0> (i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_lut<0>)
MUXCY:S->O 1 0.215 0.000 i_Core/Mcount_Si57xDivider_c_cy<0> (i_Core/Mcount_Si57xDivider_c_cy<0>) MUXCY:S->O 1 0.215 0.000 i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_cy<0> (i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_cy<0>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<1> (i_Core/Mcount_Si57xDivider_c_cy<1>) MUXCY:CI->O 1 0.023 0.000 i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_cy<1> (i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_cy<1>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<2> (i_Core/Mcount_Si57xDivider_c_cy<2>) MUXCY:CI->O 1 0.023 0.000 i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_cy<2> (i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_cy<2>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<3> (i_Core/Mcount_Si57xDivider_c_cy<3>) MUXCY:CI->O 1 0.023 0.000 i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_cy<3> (i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_cy<3>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<4> (i_Core/Mcount_Si57xDivider_c_cy<4>) MUXCY:CI->O 1 0.023 0.000 i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_cy<4> (i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_cy<4>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<5> (i_Core/Mcount_Si57xDivider_c_cy<5>) MUXCY:CI->O 18 0.235 1.158 i_Core/i_SpiMasterWB/Mcompar_TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o_cy<5> (i_Core/i_SpiMasterWB/TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<6> (i_Core/Mcount_Si57xDivider_c_cy<6>) LUT6:I4->O 4 0.250 1.139 i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In1 (i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In1)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<7> (i_Core/Mcount_Si57xDivider_c_cy<7>) LUT6:I0->O 17 0.254 1.028 i_Core/i_SpiMasterWB/_n0817_inv2 (i_Core/i_SpiMasterWB/_n0817_inv)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<8> (i_Core/Mcount_Si57xDivider_c_cy<8>) LUT3:I2->O 1 0.254 0.000 i_Core/i_SpiMasterWB/ShiftIn_qb32_31_rstpot (i_Core/i_SpiMasterWB/ShiftIn_qb32_31_rstpot)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<9> (i_Core/Mcount_Si57xDivider_c_cy<9>) FDR:D 0.074 i_Core/i_SpiMasterWB/ShiftIn_qb32_31
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<10> (i_Core/Mcount_Si57xDivider_c_cy<10>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<11> (i_Core/Mcount_Si57xDivider_c_cy<11>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<12> (i_Core/Mcount_Si57xDivider_c_cy<12>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<13> (i_Core/Mcount_Si57xDivider_c_cy<13>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<14> (i_Core/Mcount_Si57xDivider_c_cy<14>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<15> (i_Core/Mcount_Si57xDivider_c_cy<15>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<16> (i_Core/Mcount_Si57xDivider_c_cy<16>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<17> (i_Core/Mcount_Si57xDivider_c_cy<17>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<18> (i_Core/Mcount_Si57xDivider_c_cy<18>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<19> (i_Core/Mcount_Si57xDivider_c_cy<19>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<20> (i_Core/Mcount_Si57xDivider_c_cy<20>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<21> (i_Core/Mcount_Si57xDivider_c_cy<21>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<22> (i_Core/Mcount_Si57xDivider_c_cy<22>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_Si57xDivider_c_xor<23> (i_Core/Result<23>1)
FD:D 0.074 i_Core/Si57xDivider_c_23
---------------------------------------- ----------------------------------------
Total 2.365ns (1.787ns logic, 0.579ns route) Total 6.551ns (2.154ns logic, 4.396ns route)
(75.5% logic, 24.5% route) (32.9% logic, 67.1% route)
========================================================================= =========================================================================
Timing constraint: Default period analysis for Clock 'VmeSysClk_ik' Timing constraint: Default period analysis for Clock 'i_Core/i_VmeInterface/Stb_oq'
Clock period: 2.365ns (frequency: 422.770MHz)
Total number of paths / destination ports: 300 / 24
-------------------------------------------------------------------------
Delay: 2.365ns (Levels of Logic = 25)
Source: i_Core/VmeSysClkDivider_c_0 (FF)
Destination: i_Core/VmeSysClkDivider_c_23 (FF)
Source Clock: VmeSysClk_ik rising
Destination Clock: VmeSysClk_ik rising
Data Path: i_Core/VmeSysClkDivider_c_0 to i_Core/VmeSysClkDivider_c_23
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.525 0.579 i_Core/VmeSysClkDivider_c_0 (i_Core/VmeSysClkDivider_c_0)
INV:I->O 1 0.255 0.000 i_Core/Mcount_VmeSysClkDivider_c_lut<0>_INV_0 (i_Core/Mcount_VmeSysClkDivider_c_lut<0>)
MUXCY:S->O 1 0.215 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<0> (i_Core/Mcount_VmeSysClkDivider_c_cy<0>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<1> (i_Core/Mcount_VmeSysClkDivider_c_cy<1>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<2> (i_Core/Mcount_VmeSysClkDivider_c_cy<2>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<3> (i_Core/Mcount_VmeSysClkDivider_c_cy<3>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<4> (i_Core/Mcount_VmeSysClkDivider_c_cy<4>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<5> (i_Core/Mcount_VmeSysClkDivider_c_cy<5>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<6> (i_Core/Mcount_VmeSysClkDivider_c_cy<6>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<7> (i_Core/Mcount_VmeSysClkDivider_c_cy<7>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<8> (i_Core/Mcount_VmeSysClkDivider_c_cy<8>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<9> (i_Core/Mcount_VmeSysClkDivider_c_cy<9>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<10> (i_Core/Mcount_VmeSysClkDivider_c_cy<10>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<11> (i_Core/Mcount_VmeSysClkDivider_c_cy<11>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<12> (i_Core/Mcount_VmeSysClkDivider_c_cy<12>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<13> (i_Core/Mcount_VmeSysClkDivider_c_cy<13>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<14> (i_Core/Mcount_VmeSysClkDivider_c_cy<14>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<15> (i_Core/Mcount_VmeSysClkDivider_c_cy<15>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<16> (i_Core/Mcount_VmeSysClkDivider_c_cy<16>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<17> (i_Core/Mcount_VmeSysClkDivider_c_cy<17>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<18> (i_Core/Mcount_VmeSysClkDivider_c_cy<18>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<19> (i_Core/Mcount_VmeSysClkDivider_c_cy<19>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<20> (i_Core/Mcount_VmeSysClkDivider_c_cy<20>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<21> (i_Core/Mcount_VmeSysClkDivider_c_cy<21>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<22> (i_Core/Mcount_VmeSysClkDivider_c_cy<22>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VmeSysClkDivider_c_xor<23> (i_Core/Result<23>)
FD:D 0.074 i_Core/VmeSysClkDivider_c_23
----------------------------------------
Total 2.365ns (1.787ns logic, 0.579ns route)
(75.5% logic, 24.5% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'i_Core/i_VmeInterface/stb_o'
Clock period: 2.049ns (frequency: 488.019MHz) Clock period: 2.049ns (frequency: 488.019MHz)
Total number of paths / destination ports: 1 / 1 Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------- -------------------------------------------------------------------------
Delay: 2.049ns (Levels of Logic = 1) Delay: 2.049ns (Levels of Logic = 1)
Source: i_Core/i_VmeAccessMonostable/AsynchIn_ax (FF) Source: i_Core/i_VmeAccessMonostable/AsynchIn_ax (FF)
Destination: i_Core/i_VmeAccessMonostable/AsynchIn_ax (FF) Destination: i_Core/i_VmeAccessMonostable/AsynchIn_ax (FF)
Source Clock: i_Core/i_VmeInterface/stb_o rising Source Clock: i_Core/i_VmeInterface/Stb_oq rising
Destination Clock: i_Core/i_VmeInterface/stb_o rising Destination Clock: i_Core/i_VmeInterface/Stb_oq rising
Data Path: i_Core/i_VmeAccessMonostable/AsynchIn_ax to i_Core/i_VmeAccessMonostable/AsynchIn_ax Data Path: i_Core/i_VmeAccessMonostable/AsynchIn_ax to i_Core/i_VmeAccessMonostable/AsynchIn_ax
Gate Net Gate Net
...@@ -1128,50 +1038,6 @@ Delay: 2.049ns (Levels of Logic = 1) ...@@ -1128,50 +1038,6 @@ Delay: 2.049ns (Levels of Logic = 1)
Total 2.049ns (0.854ns logic, 1.195ns route) Total 2.049ns (0.854ns logic, 1.195ns route)
(41.7% logic, 58.3% route) (41.7% logic, 58.3% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'i_Core/Rst_rq'
Clock period: 2.049ns (frequency: 488.019MHz)
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 2.049ns (Levels of Logic = 1)
Source: i_Core/i_ClearMonostable/AsynchIn_ax (FF)
Destination: i_Core/i_ClearMonostable/AsynchIn_ax (FF)
Source Clock: i_Core/Rst_rq rising
Destination Clock: i_Core/Rst_rq rising
Data Path: i_Core/i_ClearMonostable/AsynchIn_ax to i_Core/i_ClearMonostable/AsynchIn_ax
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 0.616 i_Core/i_ClearMonostable/AsynchIn_ax (i_Core/i_ClearMonostable/AsynchIn_ax)
INV:I->O 1 0.255 0.579 i_Core/i_ClearMonostable/AsynchIn_ax_INV_1_o1_INV_0 (i_Core/i_ClearMonostable/AsynchIn_ax_INV_1_o)
FD:D 0.074 i_Core/i_ClearMonostable/AsynchIn_ax
----------------------------------------
Total 2.049ns (0.854ns logic, 1.195ns route)
(41.7% logic, 58.3% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'i_Core/WriteCycle'
Clock period: 2.049ns (frequency: 488.019MHz)
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 2.049ns (Levels of Logic = 1)
Source: i_Core/i_WriteCycleMonostable/AsynchIn_ax (FF)
Destination: i_Core/i_WriteCycleMonostable/AsynchIn_ax (FF)
Source Clock: i_Core/WriteCycle rising
Destination Clock: i_Core/WriteCycle rising
Data Path: i_Core/i_WriteCycleMonostable/AsynchIn_ax to i_Core/i_WriteCycleMonostable/AsynchIn_ax
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 0.616 i_Core/i_WriteCycleMonostable/AsynchIn_ax (i_Core/i_WriteCycleMonostable/AsynchIn_ax)
INV:I->O 1 0.255 0.579 i_Core/i_WriteCycleMonostable/AsynchIn_ax_INV_1_o1_INV_0 (i_Core/i_WriteCycleMonostable/AsynchIn_ax_INV_1_o)
FD:D 0.074 i_Core/i_WriteCycleMonostable/AsynchIn_ax
----------------------------------------
Total 2.049ns (0.854ns logic, 1.195ns route)
(41.7% logic, 58.3% route)
========================================================================= =========================================================================
Timing constraint: Default period analysis for Clock 'SysAppClk_ik' Timing constraint: Default period analysis for Clock 'SysAppClk_ik'
Clock period: 3.056ns (frequency: 327.221MHz) Clock period: 3.056ns (frequency: 327.221MHz)
...@@ -1195,28 +1061,33 @@ Delay: 3.056ns (Levels of Logic = 1) ...@@ -1195,28 +1061,33 @@ Delay: 3.056ns (Levels of Logic = 1)
(35.2% logic, 64.8% route) (35.2% logic, 64.8% route)
========================================================================= =========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'VcTcXo_ik' Timing constraint: Default OFFSET IN BEFORE for Clock 'Si57x_ik'
Total number of paths / destination ports: 1705 / 116 Total number of paths / destination ports: 8529 / 94
------------------------------------------------------------------------- -------------------------------------------------------------------------
Offset: 8.362ns (Levels of Logic = 6) Offset: 12.165ns (Levels of Logic = 11)
Source: VmeGa_ib5n<0> (PAD) Source: VmeGa_ib5n<0> (PAD)
Destination: i_Core/i_VmeInterface/adr_o_21 (FF) Destination: i_Core/i_VmeInterface/VmeIAckOutn_oqn (FF)
Destination Clock: VcTcXo_ik rising Destination Clock: Si57x_ik rising
Data Path: VmeGa_ib5n<0> to i_Core/i_VmeInterface/adr_o_21 Data Path: VmeGa_ib5n<0> to i_Core/i_VmeInterface/VmeIAckOutn_oqn
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF) IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
LUT6:I1->O 5 0.254 0.943 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error) LUT6:I1->O 6 0.254 0.973 i_Core/i_VmeInterface/GapError1 (i_Core/i_VmeInterface/GapError)
LUT4:I1->O 2 0.235 0.725 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o311 (N6) LUT4:I1->O 1 0.235 1.035 i_Core/i_VmeInterface/Mmux_BoardBaseAddr_b521 (i_Core/i_VmeInterface/BoardBaseAddr_b5<1>)
LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o87_SW0 (N260) LUT6:I0->O 1 0.254 0.808 i_Core/i_VmeInterface/ValidRWBA_a81 (i_Core/i_VmeInterface/ValidRWBA_a8)
LUT6:I3->O 12 0.235 0.909 i_Core/i_VmeInterface/selected (i_Core/i_VmeInterface/selected) LUT6:I3->O 1 0.235 1.035 i_Core/i_VmeInterface/ValidRWBA_a83_SW0 (N292)
LUT5:I4->O 24 0.254 1.172 i_Core/i_VmeInterface/_n0350_inv1 (i_Core/i_VmeInterface/_n0350_inv) LUT6:I0->O 3 0.254 0.879 i_Core/i_VmeInterface/ValidRWBA_a83 (i_Core/i_VmeInterface/ValidRWBA_a)
FDRE:CE 0.302 i_Core/i_VmeInterface/adr_o_0 LUT4:I1->O 1 0.235 0.580 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1_SW0 (N40)
LUT6:I5->O 9 0.254 1.285 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1 (N3)
LUT6:I0->O 1 0.254 0.000 i_Core/i_VmeInterface/State_q_NextState_a[1]_PWR_5_o_equal_44_o1_F (N398)
MUXF7:I0->O 9 0.163 0.830 i_Core/i_VmeInterface/State_q_NextState_a[1]_PWR_5_o_equal_44_o1 (i_Core/i_VmeInterface/NextState_a[1]_PWR_5_o_equal_44_o)
LUT4:I3->O 1 0.254 0.000 i_Core/i_VmeInterface/Mmux_State_q[1]_VmeDataReg_qb32[31]_wide_mux_57_OUT110 (i_Core/i_VmeInterface/State_q[1]_VmeDataReg_qb32[31]_wide_mux_57_OUT<0>)
FDRE:D 0.074 i_Core/i_VmeInterface/VmeDataReg_qb32_0
---------------------------------------- ----------------------------------------
Total 8.362ns (2.758ns logic, 5.604ns route) Total 12.165ns (3.694ns logic, 8.471ns route)
(33.0% logic, 67.0% route) (30.4% logic, 69.6% route)
========================================================================= =========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SysAppClk_ik' Timing constraint: Default OFFSET IN BEFORE for Clock 'SysAppClk_ik'
...@@ -1237,69 +1108,31 @@ Offset: 1.918ns (Levels of Logic = 1) ...@@ -1237,69 +1108,31 @@ Offset: 1.918ns (Levels of Logic = 1)
Total 1.918ns (1.302ns logic, 0.616ns route) Total 1.918ns (1.302ns logic, 0.616ns route)
(67.9% logic, 32.1% route) (67.9% logic, 32.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'VcTcXo_ik'
Total number of paths / destination ports: 190 / 94
-------------------------------------------------------------------------
Offset: 6.030ns (Levels of Logic = 2)
Source: i_Core/i_SpiMasterWB/Config1_qb32_29 (FF)
Destination: FlashSFpgaD_o (PAD)
Source Clock: VcTcXo_ik rising
Data Path: i_Core/i_SpiMasterWB/Config1_qb32_29 to FlashSFpgaD_o
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 66 0.525 1.654 i_Core/i_SpiMasterWB/Config1_qb32_29 (i_Core/i_SpiMasterWB/Config1_qb32_29)
LUT3:I2->O 11 0.254 0.882 i_Core/i_SpiMasterWB/Mmux_MoSi_o11 (FlashAFpgaD_o_OBUF)
OBUF:I->O 2.715 PllFmc1SDio_io_OBUF (PllFmc1SDio_io)
----------------------------------------
Total 6.030ns (3.494ns logic, 2.536ns route)
(57.9% logic, 42.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'VmeSysClk_ik'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 3.856ns (Levels of Logic = 1)
Source: i_Core/VmeSysClkDivider_c_23 (FF)
Destination: FpLed_onb8<6> (PAD)
Source Clock: VmeSysClk_ik rising
Data Path: i_Core/VmeSysClkDivider_c_23 to FpLed_onb8<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 0.616 i_Core/VmeSysClkDivider_c_23 (i_Core/VmeSysClkDivider_c_23)
OBUFT:T->O 2.715 FpLed_onb8_6_OBUFT (FpLed_onb8<6>)
----------------------------------------
Total 3.856ns (3.240ns logic, 0.616ns route)
(84.0% logic, 16.0% route)
========================================================================= =========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Si57x_ik' Timing constraint: Default OFFSET OUT AFTER for Clock 'Si57x_ik'
Total number of paths / destination ports: 1 / 1 Total number of paths / destination ports: 149 / 92
------------------------------------------------------------------------- -------------------------------------------------------------------------
Offset: 3.856ns (Levels of Logic = 1) Offset: 6.177ns (Levels of Logic = 2)
Source: i_Core/Si57xDivider_c_23 (FF) Source: i_Core/Rst_rq (FF)
Destination: FpLed_onb8<4> (PAD) Destination: FpLed_onb8<3> (PAD)
Source Clock: Si57x_ik rising Source Clock: Si57x_ik rising
Data Path: i_Core/Si57xDivider_c_23 to FpLed_onb8<4> Data Path: i_Core/Rst_rq to FpLed_onb8<3>
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
FD:C->Q 2 0.525 0.616 i_Core/Si57xDivider_c_23 (i_Core/Si57xDivider_c_23) FD:C->Q 569 0.525 2.104 i_Core/Rst_rq (i_Core/Rst_rq)
OBUFT:T->O 2.715 FpLed_onb8_4_OBUFT (FpLed_onb8<4>) LUT2:I1->O 1 0.254 0.579 i_Core/Si57xDivided_Rst_rq_OR_8_o_inv1 (i_Core/Si57xDivided_Rst_rq_OR_8_o_inv)
OBUFT:T->O 2.715 FpLed_onb8_3_OBUFT (FpLed_onb8<3>)
---------------------------------------- ----------------------------------------
Total 3.856ns (3.240ns logic, 0.616ns route) Total 6.177ns (3.494ns logic, 2.683ns route)
(84.0% logic, 16.0% route) (56.6% logic, 43.4% route)
========================================================================= =========================================================================
Timing constraint: Default path analysis Timing constraint: Default path analysis
Total number of paths / destination ports: 13 / 7 Total number of paths / destination ports: 21 / 9
------------------------------------------------------------------------- -------------------------------------------------------------------------
Delay: 6.896ns (Levels of Logic = 4) Delay: 6.926ns (Levels of Logic = 4)
Source: VmeGa_ib5n<0> (PAD) Source: VmeGa_ib5n<0> (PAD)
Destination: FpLed_onb8<2> (PAD) Destination: FpLed_onb8<2> (PAD)
...@@ -1308,12 +1141,12 @@ Delay: 6.896ns (Levels of Logic = 4) ...@@ -1308,12 +1141,12 @@ Delay: 6.896ns (Levels of Logic = 4)
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF) IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
LUT6:I1->O 5 0.254 0.823 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error) LUT6:I1->O 6 0.254 0.853 i_Core/i_VmeInterface/GapError1 (i_Core/i_VmeInterface/GapError)
LUT2:I0->O 1 0.250 0.579 i_Core/VmeGa_ib5n[4]_UseGa_i_OR_7_o_inv1 (i_Core/VmeGa_ib5n[4]_UseGa_i_OR_7_o_inv) LUT2:I0->O 1 0.250 0.579 i_Core/VmeGa_ib5n[4]_UseGa_i_OR_7_o_inv1 (i_Core/VmeGa_ib5n[4]_UseGa_i_OR_7_o_inv)
OBUFT:T->O 2.715 FpLed_onb8_2_OBUFT (FpLed_onb8<2>) OBUFT:T->O 2.715 FpLed_onb8_2_OBUFT (FpLed_onb8<2>)
---------------------------------------- ----------------------------------------
Total 6.896ns (4.447ns logic, 2.449ns route) Total 6.926ns (4.447ns logic, 2.479ns route)
(64.5% logic, 35.5% route) (64.2% logic, 35.8% route)
========================================================================= =========================================================================
...@@ -1321,77 +1154,43 @@ Cross Clock Domains Report: ...@@ -1321,77 +1154,43 @@ Cross Clock Domains Report:
-------------------------- --------------------------
Clock to Setup on destination clock Si57x_ik Clock to Setup on destination clock Si57x_ik
---------------+---------+---------+---------+---------+ ----------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+ ----------------------------+---------+---------+---------+---------+
Si57x_ik | 2.365| | | | Si57x_ik | 6.551| | | |
---------------+---------+---------+---------+---------+ SysAppClk_ik | 1.178| | | |
i_Core/i_VmeInterface/Stb_oq| 1.141| | | |
----------------------------+---------+---------+---------+---------+
Clock to Setup on destination clock SysAppClk_ik Clock to Setup on destination clock SysAppClk_ik
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
Si57x_ik | 3.087| | | |
SysAppClk_ik | 3.056| | | | SysAppClk_ik | 3.056| | | |
VcTcXo_ik | 3.078| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock VcTcXo_ik
---------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------+---------+---------+---------+---------+
SysAppClk_ik | 1.178| | | |
VcTcXo_ik | 8.328| | | |
i_Core/Rst_rq | 1.141| | | |
i_Core/WriteCycle | 1.141| | | |
i_Core/i_VmeInterface/stb_o| 1.141| | | |
---------------------------+---------+---------+---------+---------+
Clock to Setup on destination clock VmeSysClk_ik
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
VmeSysClk_ik | 2.365| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock i_Core/Rst_rq
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
i_Core/Rst_rq | 2.049| | | |
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
Clock to Setup on destination clock i_Core/WriteCycle Clock to Setup on destination clock i_Core/i_VmeInterface/Stb_oq
-----------------+---------+---------+---------+---------+ ----------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+ ----------------------------+---------+---------+---------+---------+
i_Core/WriteCycle| 2.049| | | | i_Core/i_VmeInterface/Stb_oq| 2.049| | | |
-----------------+---------+---------+---------+---------+ ----------------------------+---------+---------+---------+---------+
Clock to Setup on destination clock i_Core/i_VmeInterface/stb_o
---------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------+---------+---------+---------+---------+
i_Core/i_VmeInterface/stb_o| 2.049| | | |
---------------------------+---------+---------+---------+---------+
========================================================================= =========================================================================
Total REAL time to Xst completion: 16.00 secs Total REAL time to Xst completion: 17.00 secs
Total CPU time to Xst completion: 16.80 secs Total CPU time to Xst completion: 17.03 secs
--> -->
Total memory usage is 280080 kilobytes Total memory usage is 276204 kilobytes
Number of errors : 0 ( 0 filtered) Number of errors : 0 ( 0 filtered)
Number of warnings : 130 ( 0 filtered) Number of warnings : 132 ( 0 filtered)
Number of infos : 12 ( 0 filtered) Number of infos : 17 ( 0 filtered)
trunk/firmware/XilinxISE/SystemFpga/SFpga.twr
View file @ cb70c6e4
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.twx
View file @ cb70c6e4
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ucf
View file @ cb70c6e4
...@@ -699,10 +699,8 @@ NET "Si57x_ik" TNM_NET = "Si57x_ik"; ...@@ -699,10 +699,8 @@ NET "Si57x_ik" TNM_NET = "Si57x_ik";
NET "SysAppClk_ik" TNM_NET = SysAppClk_ik; NET "SysAppClk_ik" TNM_NET = SysAppClk_ik;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/20 #Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/20
NET "VcTcXo_ik" TNM_NET = VcTcXo_ik; NET "VcTcXo_ik" TNM_NET = VcTcXo_ik;
TIMESPEC TS_VcTcXo_ik = PERIOD "VcTcXo_ik" 25 MHz HIGH 50%;
NET "VmeSysClk_ik" TNM_NET = VmeSysClk_ik; NET "VmeSysClk_ik" TNM_NET = VmeSysClk_ik;
TIMESPEC TS_VmeSysClk_ik = PERIOD "VmeSysClk_ik" 40 MHz HIGH 50%; TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 120 MHz HIGH 50%;
TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 100 MHz HIGH 50%;
NET "Si57x_ikn" TNM_NET = Si57x_ikn; NET "Si57x_ikn" TNM_NET = Si57x_ikn;
TIMESPEC TS_Si57x_ikn = PERIOD "Si57x_ikn" 100 MHz HIGH 50%; TIMESPEC TS_Si57x_ikn = PERIOD "Si57x_ikn" 120 MHz HIGH 50%;
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 100 MHz HIGH 50%; TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 120 MHz HIGH 50%;
trunk/firmware/XilinxISE/SystemFpga/SFpga.unroutes
View file @ cb70c6e4
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 17:36:28 2010 Thu Jan 06 13:57:45 2011
All signals are completely routed. All signals are completely routed.
...@@ -44,12 +44,12 @@ WARNING:ParHelpers:361 - There are 50 loadless signals in this design. This desi ...@@ -44,12 +44,12 @@ WARNING:ParHelpers:361 - There are 50 loadless signals in this design. This desi
Switch_ib2<0>_IBUF Switch_ib2<0>_IBUF
Switch_ib2<1>_IBUF Switch_ib2<1>_IBUF
TempIdDQ_io_IBUF TempIdDQ_io_IBUF
VcTcXo_ik_IBUF
VmeAm_ib6<1>_IBUF VmeAm_ib6<1>_IBUF
VmeAm_ib6<2>_IBUF VmeAm_ib6<2>_IBUF
VmeDs_inb2<1>_IBUF
VmeDs_inb2<2>_IBUF
VmeP0LvdsBunchClkIn_i_IBUF VmeP0LvdsBunchClkIn_i_IBUF
VmeP0LvdsTClkIn_i_IBUF VmeP0LvdsTClkIn_i_IBUF
VmeSysClk_ik_IBUF
VmeTck_i_IBUF VmeTck_i_IBUF
VmeTdi_i_IBUF VmeTdi_i_IBUF
VmeTms_i_IBUF VmeTms_i_IBUF
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_guide.ncd
View file @ cb70c6e4
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.map
View file @ cb70c6e4
...@@ -10,7 +10,7 @@ Target Device : xc6slx150t ...@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 17:35:13 2010 Mapped Date : Thu Jan 06 13:56:29 2011
Mapping design into LUTs... Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
...@@ -87,80 +87,66 @@ Updating timing models... ...@@ -87,80 +87,66 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 14 secs Total REAL time at the beginning of Placer: 13 secs
Total CPU time at the beginning of Placer: 13 secs Total CPU time at the beginning of Placer: 12 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:b839f44f) REAL time: 18 secs Phase 1.1 Initial Placement Analysis (Checksum:efb09902) REAL time: 17 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked
and 2 are not locked. If you would like to print the names of these IOs, and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:b839f44f) REAL time: 19 secs Phase 2.7 Design Feasibility Check (Checksum:efb09902) REAL time: 17 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:b839f44f) REAL time: 19 secs Phase 3.31 Local Placement Optimization (Checksum:efb09902) REAL time: 17 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
... ...
.......
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <VmeSysClk_ik> is placed at site <PAD550>. The corresponding
BUFG component <VmeSysClk_ik_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y10>.
There is only a select set of IOBs that can use the fast path to the Clocker
buffer, and they are not being used. You may want to analyze why this problem
exists and correct it. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <VmeSysClk_ik.PAD>
allowing your design to continue. This constraint disables all clock placer
rules related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:9f9006dc) REAL time: 25 secs (Checksum:f9256882) REAL time: 24 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:9f9006dc) REAL time: 25 secs Phase 5.36 Local Placement Optimization (Checksum:f9256882) REAL time: 24 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:9f9006dc) REAL time: 25 secs Phase 6.30 Global Clock Region Assignment (Checksum:f9256882) REAL time: 24 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
... ...
Phase 7.3 Local Placement Optimization (Checksum:a3e805b0) REAL time: 26 secs Phase 7.3 Local Placement Optimization (Checksum:8dab8a31) REAL time: 25 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:9fbbfedd) REAL time: 26 secs Phase 8.5 Local Placement Optimization (Checksum:f9473fcd) REAL time: 25 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
............. ....
....... ................
Phase 9.8 Global Placement (Checksum:2989ec26) REAL time: 29 secs ..............................
.........
Phase 9.8 Global Placement (Checksum:b93c6135) REAL time: 30 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:2989ec26) REAL time: 29 secs Phase 10.5 Local Placement Optimization (Checksum:b93c6135) REAL time: 30 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:7e859587) REAL time: 31 secs Phase 11.18 Placement Optimization (Checksum:7f5491fd) REAL time: 35 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:7e859587) REAL time: 31 secs Phase 12.5 Local Placement Optimization (Checksum:7f5491fd) REAL time: 35 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:9557604f) REAL time: 31 secs Phase 13.34 Placement Validation (Checksum:d2ef8286) REAL time: 35 secs
Total REAL time to Placer completion: 36 secs Total REAL time to Placer completion: 40 secs
Total CPU time to Placer completion: 35 secs Total CPU time to Placer completion: 39 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_Core/WriteCycle is WARNING:PhysDesignRules:372 - Gated clock. Clock net
sourced by a combinatorial pin. This is not good design practice. Use the CE i_Core/i_VmeInterface/Stb_oq is sourced by a combinatorial pin. This is not
pin to control the loading of data into the flip-flop. good design practice. Use the CE pin to control the loading of data into the
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The flip-flop.
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
...@@ -207,6 +193,8 @@ WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The ...@@ -207,6 +193,8 @@ WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeSysClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The
...@@ -237,6 +225,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is ...@@ -237,6 +225,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VcTcXo_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
...@@ -264,18 +254,18 @@ Design Summary ...@@ -264,18 +254,18 @@ Design Summary
Design Summary: Design Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 86 Number of warnings: 85
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 834 out of 184,304 1% Number of Slice Registers: 784 out of 184,304 1%
Number used as Flip Flops: 834 Number used as Flip Flops: 784
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 965 out of 92,152 1% Number of Slice LUTs: 878 out of 92,152 1%
Number used as logic: 934 out of 92,152 1% Number used as logic: 851 out of 92,152 1%
Number using O6 output only: 579 Number using O6 output only: 622
Number using O5 output only: 187 Number using O5 output only: 83
Number using O5 and O6: 168 Number using O5 and O6: 146
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1% Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
...@@ -284,21 +274,21 @@ Slice Logic Utilization: ...@@ -284,21 +274,21 @@ Slice Logic Utilization:
Number using O5 and O6: 4 Number using O5 and O6: 4
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 6 Number used as Shift Register: 6
Number using O6 output only: 6 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 2
Number used exclusively as route-thrus: 17 Number used exclusively as route-thrus: 13
Number with same-slice register load: 7 Number with same-slice register load: 8
Number with same-slice carry load: 10 Number with same-slice carry load: 5
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 383 out of 23,038 1% Number of occupied Slices: 353 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,137 Number of LUT Flip Flop pairs used: 1,041
Number with an unused Flip Flop: 369 out of 1,137 32% Number with an unused Flip Flop: 330 out of 1,041 31%
Number with an unused LUT: 172 out of 1,137 15% Number with an unused LUT: 163 out of 1,041 15%
Number of fully used LUT-FF pairs: 596 out of 1,137 52% Number of fully used LUT-FF pairs: 548 out of 1,041 52%
Number of unique control sets: 34 Number of unique control sets: 26
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 76 out of 184,304 1% to control set restrictions: 76 out of 184,304 1%
...@@ -319,8 +309,8 @@ Specific Feature Utilization: ...@@ -319,8 +309,8 @@ Specific Feature Utilization:
Number of RAMB8BWERs: 0 out of 536 0% Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25% Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 4 Number used as BUFGs: 2
Number used as BUFGMUX: 0 Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0% Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0% Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
...@@ -341,11 +331,11 @@ Specific Feature Utilization: ...@@ -341,11 +331,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.00 Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 629 MB Peak Memory Usage: 627 MB
Total REAL time to MAP completion: 38 secs Total REAL time to MAP completion: 41 secs
Total CPU time to MAP completion: 36 secs Total CPU time to MAP completion: 41 secs
Mapping completed. Mapping completed.
See MAP report file "SFpga_map.mrp" for details. See MAP report file "SFpga_map.mrp" for details.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.mrp
View file @ cb70c6e4
...@@ -10,23 +10,23 @@ Target Device : xc6slx150t ...@@ -10,23 +10,23 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 17:35:13 2010 Mapped Date : Thu Jan 06 13:56:29 2011
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 86 Number of warnings: 85
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 834 out of 184,304 1% Number of Slice Registers: 784 out of 184,304 1%
Number used as Flip Flops: 834 Number used as Flip Flops: 784
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 965 out of 92,152 1% Number of Slice LUTs: 878 out of 92,152 1%
Number used as logic: 934 out of 92,152 1% Number used as logic: 851 out of 92,152 1%
Number using O6 output only: 579 Number using O6 output only: 622
Number using O5 output only: 187 Number using O5 output only: 83
Number using O5 and O6: 168 Number using O5 and O6: 146
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1% Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
...@@ -35,21 +35,21 @@ Slice Logic Utilization: ...@@ -35,21 +35,21 @@ Slice Logic Utilization:
Number using O5 and O6: 4 Number using O5 and O6: 4
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 6 Number used as Shift Register: 6
Number using O6 output only: 6 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 2
Number used exclusively as route-thrus: 17 Number used exclusively as route-thrus: 13
Number with same-slice register load: 7 Number with same-slice register load: 8
Number with same-slice carry load: 10 Number with same-slice carry load: 5
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 383 out of 23,038 1% Number of occupied Slices: 353 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,137 Number of LUT Flip Flop pairs used: 1,041
Number with an unused Flip Flop: 369 out of 1,137 32% Number with an unused Flip Flop: 330 out of 1,041 31%
Number with an unused LUT: 172 out of 1,137 15% Number with an unused LUT: 163 out of 1,041 15%
Number of fully used LUT-FF pairs: 596 out of 1,137 52% Number of fully used LUT-FF pairs: 548 out of 1,041 52%
Number of unique control sets: 34 Number of unique control sets: 26
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 76 out of 184,304 1% to control set restrictions: 76 out of 184,304 1%
...@@ -70,8 +70,8 @@ Specific Feature Utilization: ...@@ -70,8 +70,8 @@ Specific Feature Utilization:
Number of RAMB8BWERs: 0 out of 536 0% Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25% Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 4 Number used as BUFGs: 2
Number used as BUFGMUX: 0 Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0% Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0% Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
...@@ -92,11 +92,11 @@ Specific Feature Utilization: ...@@ -92,11 +92,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.00 Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 629 MB Peak Memory Usage: 627 MB
Total REAL time to MAP completion: 38 secs Total REAL time to MAP completion: 41 secs
Total CPU time to MAP completion: 36 secs Total CPU time to MAP completion: 41 secs
Table of Contents Table of Contents
----------------- -----------------
...@@ -187,25 +187,10 @@ WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port ...@@ -187,25 +187,10 @@ WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed. AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
VAdjInhibit_ozn has been removed. VAdjInhibit_ozn has been removed.
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found WARNING:PhysDesignRules:372 - Gated clock. Clock net
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock i_Core/i_VmeInterface/Stb_oq is sourced by a combinatorial pin. This is not
IOB component <VmeSysClk_ik> is placed at site <PAD550>. The corresponding good design practice. Use the CE pin to control the loading of data into the
BUFG component <VmeSysClk_ik_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y10>. flip-flop.
There is only a select set of IOBs that can use the fast path to the Clocker
buffer, and they are not being used. You may want to analyze why this problem
exists and correct it. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <VmeSysClk_ik.PAD>
allowing your design to continue. This constraint disables all clock placer
rules related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_Core/WriteCycle is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
...@@ -252,6 +237,8 @@ WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The ...@@ -252,6 +237,8 @@ WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeSysClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The
...@@ -282,6 +269,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is ...@@ -282,6 +269,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VcTcXo_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
...@@ -306,14 +295,14 @@ WARNING:PhysDesignRules:367 - The signal ...@@ -306,14 +295,14 @@ WARNING:PhysDesignRules:367 - The signal
Section 3 - Informational Section 3 - Informational
------------------------- -------------------------
INFO:LIT:243 - Logical network N452 has no load. INFO:LIT:243 - Logical network N504 has no load.
INFO:LIT:395 - The above info message is repeated 54 more times for the INFO:LIT:395 - The above info message is repeated 54 more times for the
following (max. 5 shown): following (max. 5 shown):
N454, N506,
VmeAm_ib6<2>_IBUF, VmeAm_ib6<2>_IBUF,
VmeAm_ib6<1>_IBUF, VmeAm_ib6<1>_IBUF,
VmeDs_inb2<2>_IBUF, Switch_ib2<1>_IBUF,
VmeDs_inb2<1>_IBUF Switch_ib2<0>_IBUF
To see the details of these info messages, please use the -detail switch. To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew INFO:LIT:244 - All of the single ended outputs in this design are using slew
...@@ -323,6 +312,8 @@ INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: ...@@ -323,6 +312,8 @@ INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius) 0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts) 1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ncd
View file @ cb70c6e4
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ngm
View file @ cb70c6e4
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.xrpt
View file @ cb70c6e4
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Mon Dec 20 17:35:52 2010"> <application stringID="Map" timeStamp="Thu Jan 06 13:57:11 2011">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
...@@ -64,16 +64,16 @@ ...@@ -64,16 +64,16 @@
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx150t-fgg676-3"/> <item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx150t-fgg676-3"/>
</section> </section>
<task stringID="MAP_PACK_REPORT"> <task stringID="MAP_PACK_REPORT">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="834"> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="784">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="834"/> <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="784"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="958"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="870">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="187"/> <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="83"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="579"/> <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="622"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="168"/> <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="146"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
...@@ -84,13 +84,13 @@ ...@@ -84,13 +84,13 @@
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="6"/> <item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="4"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="2"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="10"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="5"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="10"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="5"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item> </item>
<item AVAILABLE="396" dataType="int" stringID="MAP_AGG_BONDED_IO" value="331"/> <item AVAILABLE="396" dataType="int" stringID="MAP_AGG_BONDED_IO" value="331"/>
...@@ -115,22 +115,22 @@ ...@@ -115,22 +115,22 @@
<section stringID="MAP_DESIGN_SUMMARY"> <section stringID="MAP_DESIGN_SUMMARY">
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/> <item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/> <item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="86"/> <item dataType="int" stringID="MAP_NUM_WARNINGS" value="85"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="644020"/> <item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="642192"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="38 secs "/> <item stringID="MAP_TOTAL_REAL_TIME" value="41 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="36 secs "/> <item stringID="MAP_TOTAL_CPU_TIME" value="41 secs "/>
</section> </section>
<section stringID="MAP_SLICE_REPORTING"> <section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="834"> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="784">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="834"/> <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="784"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="965"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="878">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="187"/> <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="83"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="579"/> <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="622"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="168"/> <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="146"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
...@@ -141,24 +141,24 @@ ...@@ -141,24 +141,24 @@
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="6"/> <item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="4"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="2"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="10"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="5"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="7"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="8"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="7"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="8"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="10"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="5"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item> </item>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="383"> <item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="353">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="88"/> <item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="59"/>
<item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/> <item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="291"/> <item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="290"/>
</item> </item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1137"> <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1041">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="369"/> <item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="330"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="172"/> <item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="163"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="596"/> <item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="548"/>
</item> </item>
</section> </section>
<section stringID="MAP_IOB_REPORTING"> <section stringID="MAP_IOB_REPORTING">
...@@ -197,7 +197,7 @@ ...@@ -197,7 +197,7 @@
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/> <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
</section> </section>
<section stringID="MAP_BUFG_DATA"> <section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="4"/> <item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/> <item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/> <item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
</section> </section>
...@@ -2543,7 +2543,7 @@ ...@@ -2543,7 +2543,7 @@
</section> </section>
<section stringID="MAP_RPM_MACROS"> <section stringID="MAP_RPM_MACROS">
<section stringID="MAP_SHAPE_SECTION"> <section stringID="MAP_SHAPE_SECTION">
<item dataType="int" stringID="MAP_NUM_SHAPE" value="13"/> <item dataType="int" stringID="MAP_NUM_SHAPE" value="8"/>
</section> </section>
</section> </section>
<section stringID="MAP_GUIDE_REPORT"/> <section stringID="MAP_GUIDE_REPORT"/>
...@@ -2552,7 +2552,7 @@ ...@@ -2552,7 +2552,7 @@
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/> <section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
<section stringID="MAP_GENERAL_CONFIG_DATA"/> <section stringID="MAP_GENERAL_CONFIG_DATA"/>
<section stringID="MAP_CONTROL_SET_INFORMATION"> <section stringID="MAP_CONTROL_SET_INFORMATION">
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="34"/> <item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="26"/>
<tree stringID="MAP_CONTROL_SET_HIERARCHY"> <tree stringID="MAP_CONTROL_SET_HIERARCHY">
<property stringID="MAP_CLOCK_SIGNAL"/> <property stringID="MAP_CLOCK_SIGNAL"/>
<property stringID="MAP_RESET_SIGNAL"/> <property stringID="MAP_RESET_SIGNAL"/>
...@@ -2584,7 +2584,7 @@ ...@@ -2584,7 +2584,7 @@
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/> <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
</section> </section>
<section stringID="MAP_BUFG_DATA"> <section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="4"/> <item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/> <item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/> <item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/> <item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_ngdbuild.xrpt
View file @ cb70c6e4
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Mon Dec 20 17:35:12 2010"> <application stringID="NgdBuild" timeStamp="Thu Jan 06 13:56:28 2011">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
...@@ -61,75 +61,75 @@ ...@@ -61,75 +61,75 @@
<section stringID="NGDBUILD_DESIGN_SUMMARY"> <section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/> <item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/> <item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="14"/> <item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="18"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/> <item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/> <item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section> </section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY"> <section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="195"/> <item dataType="int" stringID="NGDBUILD_NUM_FD" value="165"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="102"/> <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="104"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/> <item dataType="int" stringID="NGDBUILD_NUM_FDR" value="170"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="342"/> <item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="310"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/> <item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/> <item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="76"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="77"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="32"/> <item dataType="int" stringID="NGDBUILD_NUM_INV" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="32"/> <item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUFDS" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_IOBUFDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="197"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="86"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="168"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="211"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="130"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="149"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="116"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="85"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="123"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="298"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="284"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="220"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="128"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="28"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="154"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="32"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="30"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="216"/> <item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="121"/>
</section> </section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY"> <section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="4"/> <item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="195"/> <item dataType="int" stringID="NGDBUILD_NUM_FD" value="165"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="102"/> <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="104"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/> <item dataType="int" stringID="NGDBUILD_NUM_FDR" value="170"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="342"/> <item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="310"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/> <item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/> <item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="157"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="158"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFDS" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUFDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="32"/> <item dataType="int" stringID="NGDBUILD_NUM_INV" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="197"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="86"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="168"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="211"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="130"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="149"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="116"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="85"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="123"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="298"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="284"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="220"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="128"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="28"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="154"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="64"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="62"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="216"/> <item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="121"/>
</section> </section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY"> <section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/> <section stringID="NGDBUILD_CORE_INSTANCES"/>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.csv
View file @ cb70c6e4
#Release 12.3 - par M.70d (nt64) #Release 12.3 - par M.70d (nt64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. #Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Mon Dec 20 17:36:28 2010 #Thu Jan 06 13:57:44 2011
# #
## NOTE: This file is designed to be imported into a spreadsheet program ## NOTE: This file is designed to be imported into a spreadsheet program
...@@ -543,7 +543,7 @@ R1,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,, ...@@ -543,7 +543,7 @@ R1,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,,
R2,,IOBM,IO_L44P_GCLK21_M3A5_3,UNUSED,,3,,,,,,,,, R2,,IOBM,IO_L44P_GCLK21_M3A5_3,UNUSED,,3,,,,,,,,,
R3,FpLed_onb8<2>,IOB,IO_L52N_M3A9_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE, R3,FpLed_onb8<2>,IOB,IO_L52N_M3A9_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R4,FpLed_onb8<1>,IOB,IO_L52P_M3A8_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE, R4,FpLed_onb8<1>,IOB,IO_L52P_M3A8_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R5,FpLed_onb8<4>,IOB,IO_L50N_M3BA2_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE, R5,FpLed_onb8<4>,IOB,IO_L50N_M3BA2_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R6,SysAppClk_ik,IOB,IO_L43N_GCLK22_IRDY2_M3CASN_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, R6,SysAppClk_ik,IOB,IO_L43N_GCLK22_IRDY2_M3CASN_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
R7,SysAppClk_ok,IOB,IO_L43P_GCLK23_M3RASN_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE, R7,SysAppClk_ok,IOB,IO_L43P_GCLK23_M3RASN_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R8,ManualAddress_ib5<0>,IOB,IO_L45P_M3A3_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, R8,ManualAddress_ib5<0>,IOB,IO_L45P_M3A3_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
...@@ -593,7 +593,7 @@ T25,,,VCCO_1,,,1,,,,,1.50,,,, ...@@ -593,7 +593,7 @@ T25,,,VCCO_1,,,1,,,,,1.50,,,,
T26,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,, T26,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,,
U1,Fmc2PrsntM2C_in,IOB,IO_L40N_M3DQ7_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, U1,Fmc2PrsntM2C_in,IOB,IO_L40N_M3DQ7_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
U2,Fmc2PGC2M_in,IOB,IO_L40P_M3DQ6_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE, U2,Fmc2PGC2M_in,IOB,IO_L40P_M3DQ6_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U3,FpLed_onb8<5>,IOB,IO_L10N_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE, U3,FpLed_onb8<5>,IOB,IO_L10N_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U4,FpLed_onb8<6>,IOB,IO_L10P_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE, U4,FpLed_onb8<6>,IOB,IO_L10P_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U5,AFpgaProgD_iob8<4>,IOB,IO_L46P_M3CLK_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, U5,AFpgaProgD_iob8<4>,IOB,IO_L46P_M3CLK_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
U6,,,VCCAUX,,,,,,,,2.5,,,, U6,,,VCCAUX,,,,,,,,2.5,,,,
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.txt
View file @ cb70c6e4
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 17:36:28 2010 Thu Jan 06 13:57:44 2011
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
...@@ -544,7 +544,7 @@ Pinout by Pin Number: ...@@ -544,7 +544,7 @@ Pinout by Pin Number:
|R2 | |IOBM |IO_L44P_GCLK21_M3A5_3 |UNUSED | |3 | | | | | | | | | |R2 | |IOBM |IO_L44P_GCLK21_M3A5_3 |UNUSED | |3 | | | | | | | | |
|R3 |FpLed_onb8<2> |IOB |IO_L52N_M3A9_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE | |R3 |FpLed_onb8<2> |IOB |IO_L52N_M3A9_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|R4 |FpLed_onb8<1> |IOB |IO_L52P_M3A8_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE | |R4 |FpLed_onb8<1> |IOB |IO_L52P_M3A8_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|R5 |FpLed_onb8<4> |IOB |IO_L50N_M3BA2_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE | |R5 |FpLed_onb8<4> |IOB |IO_L50N_M3BA2_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|R6 |SysAppClk_ik |IOB |IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | |R6 |SysAppClk_ik |IOB |IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|R7 |SysAppClk_ok |IOB |IO_L43P_GCLK23_M3RASN_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE | |R7 |SysAppClk_ok |IOB |IO_L43P_GCLK23_M3RASN_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|R8 |ManualAddress_ib5<0> |IOB |IO_L45P_M3A3_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | |R8 |ManualAddress_ib5<0> |IOB |IO_L45P_M3A3_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
...@@ -594,7 +594,7 @@ Pinout by Pin Number: ...@@ -594,7 +594,7 @@ Pinout by Pin Number:
|T26 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | | |T26 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | |
|U1 |Fmc2PrsntM2C_in |IOB |IO_L40N_M3DQ7_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | |U1 |Fmc2PrsntM2C_in |IOB |IO_L40N_M3DQ7_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|U2 |Fmc2PGC2M_in |IOB |IO_L40P_M3DQ6_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE | |U2 |Fmc2PGC2M_in |IOB |IO_L40P_M3DQ6_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|U3 |FpLed_onb8<5> |IOB |IO_L10N_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE | |U3 |FpLed_onb8<5> |IOB |IO_L10N_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|U4 |FpLed_onb8<6> |IOB |IO_L10P_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE | |U4 |FpLed_onb8<6> |IOB |IO_L10P_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|U5 |AFpgaProgD_iob8<4> |IOB |IO_L46P_M3CLK_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | |U5 |AFpgaProgD_iob8<4> |IOB |IO_L46P_M3CLK_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|U6 | | |VCCAUX | | | | | | | |2.5 | | | | |U6 | | |VCCAUX | | | | | | | |2.5 | | | |
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_par.xrpt
View file @ cb70c6e4
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Mon Dec 20 17:36:03 2010"> <application stringID="par" timeStamp="Thu Jan 06 13:57:22 2011">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
...@@ -59,12 +59,12 @@ ...@@ -59,12 +59,12 @@
</task> </task>
<task stringID="PAR_PAR"> <task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY"> <section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="32 secs "/> <item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="29 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="30 secs "/> <item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="29 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/> <item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/> <item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="35 secs "/> <item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="31 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="33 secs "/> <item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="31 secs "/>
</section> </section>
</task> </task>
<task stringID="PAR_par"> <task stringID="PAR_par">
...@@ -79,64 +79,30 @@ ...@@ -79,64 +79,30 @@
<column label="Net Skew(ns)" stringID="NET_SKEW"/> <column label="Net Skew(ns)" stringID="NET_SKEW"/>
<column label="Max Delay(ns)" stringID="MAX_DELAY"/> <column label="Max Delay(ns)" stringID="MAX_DELAY"/>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item label="Clock Net" stringID="CLOCK_NET" value="VcTcXo_ik_IBUF_BUFG"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y16"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="210.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.329000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.697000"/>
</row>
<row stringID="row" value="2">
<item label="Clock Net" stringID="CLOCK_NET" value="Si57x_BUFG"/> <item label="Clock Net" stringID="CLOCK_NET" value="Si57x_BUFG"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/> <item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y4"/> <item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y4"/>
<item label="Locked" stringID="LOCKED" value="No"/> <item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="6.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="218.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.008000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.316000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.686000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.696000"/>
</row> </row>
<row stringID="row" value="3"> <row stringID="row" value="2">
<item label="Clock Net" stringID="CLOCK_NET" value="VmeSysClk_ik_BUFGP"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y10"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="6.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.084000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.639000"/>
</row>
<row stringID="row" value="4">
<item label="Clock Net" stringID="CLOCK_NET" value="SysAppClk_ik_BUFGP"/> <item label="Clock Net" stringID="CLOCK_NET" value="SysAppClk_ik_BUFGP"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/> <item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y14"/> <item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y14"/>
<item label="Locked" stringID="LOCKED" value="No"/> <item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="16.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="16.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.188000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.057000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.690000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.693000"/>
</row>
<row stringID="row" value="5">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/Rst_rq"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="197.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="3.235000"/>
</row>
<row stringID="row" value="6">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/WriteCycle"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="1.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.542000"/>
</row> </row>
<row stringID="row" value="7"> <row stringID="row" value="3">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/i_VmeInterface/stb_o"/> <item label="Clock Net" stringID="CLOCK_NET" value="i_Core/i_VmeInterface/Stb_oq"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/> <item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="Local"/> <item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="19.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="18.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="4.912000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.316000"/>
</row> </row>
</table> </table>
</section> </section>
...@@ -4905,7 +4871,7 @@ ...@@ -4905,7 +4871,7 @@
<item label="Signal&#xA;Name" stringID="Signal_Name" value="FpLed_onb8&lt;4>"/> <item label="Signal&#xA;Name" stringID="Signal_Name" value="FpLed_onb8&lt;4>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/> <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L50N_M3BA2_3"/> <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L50N_M3BA2_3"/>
<item stringID="Direction" value="TRISTATE"/> <item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/> <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/> <item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
...@@ -5329,7 +5295,7 @@ ...@@ -5329,7 +5295,7 @@
<item label="Signal&#xA;Name" stringID="Signal_Name" value="FpLed_onb8&lt;5>"/> <item label="Signal&#xA;Name" stringID="Signal_Name" value="FpLed_onb8&lt;5>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/> <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L10N_3"/> <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L10N_3"/>
<item stringID="Direction" value="TRISTATE"/> <item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/> <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/> <item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
...@@ -6295,7 +6261,7 @@ ...@@ -6295,7 +6261,7 @@
</task> </task>
</application> </application>
<application stringID="Par" timeStamp="Mon Dec 20 17:36:04 2010"> <application stringID="Par" timeStamp="Thu Jan 06 13:57:22 2011">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
...@@ -6341,16 +6307,16 @@ ...@@ -6341,16 +6307,16 @@
</section> </section>
<task label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION"> <task label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION">
<section stringID="PAR_SLICE_REPORTING"> <section stringID="PAR_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="834"> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="784">
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="834"/> <item dataType="int" stringID="PAR_NUM_SLICE_FF" value="784"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCH" value="0"/> <item dataType="int" stringID="PAR_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="965"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="878">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="187"/> <item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="83"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="579"/> <item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="622"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="168"/> <item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="146"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/> <item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/> <item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/> <item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/>
...@@ -6361,24 +6327,24 @@ ...@@ -6361,24 +6327,24 @@
<item dataType="int" stringID="PAR_NUM_SPRAM_O6ONLY" value="0"/> <item dataType="int" stringID="PAR_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_SPRAM_O5ANDO6" value="0"/> <item dataType="int" stringID="PAR_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_SRL_O5ONLY" value="0"/> <item dataType="int" stringID="PAR_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="6"/> <item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="4"/>
<item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="0"/> <item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="2"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="10"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="5"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="7"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="8"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="7"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="8"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="10"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="5"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item> </item>
<item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="383"> <item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="353">
<item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="88"/> <item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="59"/>
<item AVAILABLE="5420" dataType="int" stringID="PAR_NUM_SLICEM" value="4"/> <item AVAILABLE="5420" dataType="int" stringID="PAR_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="291"/> <item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="290"/>
</item> </item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1137"> <item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1041">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="369"/> <item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="330"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="172"/> <item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="163"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="596"/> <item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="548"/>
</item> </item>
</section> </section>
<section stringID="PAR_IOB_REPORTING"> <section stringID="PAR_IOB_REPORTING">
...@@ -6417,7 +6383,7 @@ ...@@ -6417,7 +6383,7 @@
<item AVAILABLE="1" dataType="int" stringID="PAR_NUM_SUSPEND_SYNC" value="0"/> <item AVAILABLE="1" dataType="int" stringID="PAR_NUM_SUSPEND_SYNC" value="0"/>
</section> </section>
<section stringID="PAR_BUFG_DATA"> <section stringID="PAR_BUFG_DATA">
<item dataType="int" stringID="PAR_NUM_BUFG" value="4"/> <item dataType="int" stringID="PAR_NUM_BUFG" value="2"/>
<item dataType="int" stringID="PAR_NUM_BUFGMUX" value="0"/> <item dataType="int" stringID="PAR_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="PAR_AVAILABLE" value="16"/> <item dataType="int" stringID="PAR_AVAILABLE" value="16"/>
</section> </section>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.html
View file @ cb70c6e4
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (12/20/2010 - 17:37:16)</B></TD></TR> <TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (01/06/2011 - 13:58:43)</B></TD></TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>SystemFpga.xise</TD> <TD>SystemFpga.xise</TD>
...@@ -25,7 +25,7 @@ No Errors</TD> ...@@ -25,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD> <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/*.xmsgs?&DataKey=Warning'>334 Warnings (0 new)</A></TD> <TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/*.xmsgs?&DataKey=Warning'>339 Warnings (4 new)</A></TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
...@@ -60,13 +60,13 @@ System Settings</A> ...@@ -60,13 +60,13 @@ System Settings</A>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> <TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>834</TD> <TD ALIGN=RIGHT>784</TD>
<TD ALIGN=RIGHT>184,304</TD> <TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>834</TD> <TD ALIGN=RIGHT>784</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -90,31 +90,31 @@ System Settings</A> ...@@ -90,31 +90,31 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>965</TD> <TD ALIGN=RIGHT>878</TD>
<TD ALIGN=RIGHT>92,152</TD> <TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>934</TD> <TD ALIGN=RIGHT>851</TD>
<TD ALIGN=RIGHT>92,152</TD> <TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>579</TD> <TD ALIGN=RIGHT>622</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>187</TD> <TD ALIGN=RIGHT>83</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>168</TD> <TD ALIGN=RIGHT>146</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -168,7 +168,7 @@ System Settings</A> ...@@ -168,7 +168,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>6</TD> <TD ALIGN=RIGHT>4</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -180,25 +180,25 @@ System Settings</A> ...@@ -180,25 +180,25 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>17</TD> <TD ALIGN=RIGHT>13</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>7</TD> <TD ALIGN=RIGHT>8</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
<TD ALIGN=RIGHT>10</TD> <TD ALIGN=RIGHT>5</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -210,37 +210,37 @@ System Settings</A> ...@@ -210,37 +210,37 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>383</TD> <TD ALIGN=RIGHT>353</TD>
<TD ALIGN=RIGHT>23,038</TD> <TD ALIGN=RIGHT>23,038</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>1,137</TD> <TD ALIGN=RIGHT>1,041</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>369</TD> <TD ALIGN=RIGHT>330</TD>
<TD ALIGN=RIGHT>1,137</TD> <TD ALIGN=RIGHT>1,041</TD>
<TD ALIGN=RIGHT>32%</TD> <TD ALIGN=RIGHT>31%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>172</TD> <TD ALIGN=RIGHT>163</TD>
<TD ALIGN=RIGHT>1,137</TD> <TD ALIGN=RIGHT>1,041</TD>
<TD ALIGN=RIGHT>15%</TD> <TD ALIGN=RIGHT>15%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>596</TD> <TD ALIGN=RIGHT>548</TD>
<TD ALIGN=RIGHT>1,137</TD> <TD ALIGN=RIGHT>1,041</TD>
<TD ALIGN=RIGHT>52%</TD> <TD ALIGN=RIGHT>52%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
<TD ALIGN=RIGHT>34</TD> <TD ALIGN=RIGHT>26</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -300,13 +300,13 @@ System Settings</A> ...@@ -300,13 +300,13 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
<TD ALIGN=RIGHT>4</TD> <TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>16</TD> <TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>25%</TD> <TD ALIGN=RIGHT>12%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
<TD ALIGN=RIGHT>4</TD> <TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -426,7 +426,7 @@ System Settings</A> ...@@ -426,7 +426,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>3.00</TD> <TD ALIGN=RIGHT>3.41</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -463,23 +463,23 @@ System Settings</A> ...@@ -463,23 +463,23 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:23:02 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>130 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>12 Infos (2 new)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu 6. Jan 13:56:06 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>132 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>17 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:35:12 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>14 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu 6. Jan 13:56:28 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>18 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:35:52 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>86 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (0 new)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu 6. Jan 13:57:11 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>85 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>10 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:36:29 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>52 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu 6. Jan 13:57:45 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>52 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR> <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:36:41 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu 6. Jan 13:57:57 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:37:11 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>52 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu 6. Jan 13:58:26 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>52 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE> </TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu 16. Dec 17:57:34 2010</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu 16. Dec 17:57:34 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed 15. Dec 15:16:36 2010</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed 15. Dec 15:16:36 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon 20. Dec 17:37:11 2010</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu 6. Jan 13:58:27 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon 20. Dec 17:37:16 2010</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu 6. Jan 13:58:42 2011</TD></TR>
</TABLE> </TABLE>
<br><center><b>Date Generated:</b> 12/20/2010 - 17:37:17</center> <br><center><b>Date Generated:</b> 01/06/2011 - 13:58:43</center>
</BODY></HTML> </BODY></HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.xml
View file @ cb70c6e4
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DesignSummary rev="27"> <DesignSummary rev="51">
<CmdHistory> <CmdHistory>
</CmdHistory> </CmdHistory>
</DesignSummary> </DesignSummary>
trunk/firmware/XilinxISE/SystemFpga/SFpga_usage.xml
View file @ cb70c6e4
...@@ -4,803 +4,811 @@ ...@@ -4,803 +4,811 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DeviceUsageSummary rev="27"> <DeviceUsageSummary rev="51">
<DesignStatistics TimeStamp="Mon Dec 20 17:37:10 2010"><group name="NetStatistics"> <DesignStatistics TimeStamp="Thu Jan 06 13:58:26 2011"><group name="NetStatistics">
<item name="NumNets_Active" rev="27"> <item name="NumNets_Active" rev="51">
<attrib name="value" value="1908"/></item> <attrib name="value" value="1763"/></item>
<item name="NumNets_Gnd" rev="27"> <item name="NumNets_Gnd" rev="51">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="27"> <item name="NumNets_Vcc" rev="51">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="27"> <item name="NumNodesOfType_Active_BOUNCEACROSS" rev="51">
<attrib name="value" value="25"/></item> <attrib name="value" value="29"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="27"> <item name="NumNodesOfType_Active_BOUNCEIN" rev="51">
<attrib name="value" value="200"/></item> <attrib name="value" value="224"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="27"> <item name="NumNodesOfType_Active_BUFGOUT" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="27"> <item name="NumNodesOfType_Active_BUFHINP2OUT" rev="51">
<attrib name="value" value="20"/></item> <attrib name="value" value="14"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="27"> <item name="NumNodesOfType_Active_CLKPIN" rev="51">
<attrib name="value" value="241"/></item> <attrib name="value" value="235"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="27"> <item name="NumNodesOfType_Active_CLKPINFEED" rev="51">
<attrib name="value" value="26"/></item> <attrib name="value" value="14"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="27"> <item name="NumNodesOfType_Active_CNTRLPIN" rev="51">
<attrib name="value" value="287"/></item> <attrib name="value" value="270"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="27"> <item name="NumNodesOfType_Active_DOUBLE" rev="51">
<attrib name="value" value="2086"/></item> <attrib name="value" value="1968"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="27"> <item name="NumNodesOfType_Active_GENERIC" rev="51">
<attrib name="value" value="354"/></item> <attrib name="value" value="353"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="27"> <item name="NumNodesOfType_Active_GLOBAL" rev="51">
<attrib name="value" value="181"/></item> <attrib name="value" value="136"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="27"> <item name="NumNodesOfType_Active_INPUT" rev="51">
<attrib name="value" value="60"/></item> <attrib name="value" value="38"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="27"> <item name="NumNodesOfType_Active_IOBIN2OUT" rev="51">
<attrib name="value" value="243"/></item> <attrib name="value" value="242"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="27"> <item name="NumNodesOfType_Active_IOBOUTPUT" rev="51">
<attrib name="value" value="243"/></item> <attrib name="value" value="242"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="27"> <item name="NumNodesOfType_Active_LUTINPUT" rev="51">
<attrib name="value" value="3723"/></item> <attrib name="value" value="3496"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="27"> <item name="NumNodesOfType_Active_OUTBOUND" rev="51">
<attrib name="value" value="1593"/></item> <attrib name="value" value="1466"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="27"> <item name="NumNodesOfType_Active_OUTPUT" rev="51">
<attrib name="value" value="1471"/></item> <attrib name="value" value="1307"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="27"> <item name="NumNodesOfType_Active_PADINPUT" rev="51">
<attrib name="value" value="137"/></item> <attrib name="value" value="135"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="27"> <item name="NumNodesOfType_Active_PADOUTPUT" rev="51">
<attrib name="value" value="114"/></item> <attrib name="value" value="114"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="27"> <item name="NumNodesOfType_Active_PINBOUNCE" rev="51">
<attrib name="value" value="839"/></item> <attrib name="value" value="773"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="27"> <item name="NumNodesOfType_Active_PINFEED" rev="51">
<attrib name="value" value="4266"/></item> <attrib name="value" value="4025"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="27"> <item name="NumNodesOfType_Active_QUAD" rev="51">
<attrib name="value" value="5699"/></item> <attrib name="value" value="5651"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="27"> <item name="NumNodesOfType_Active_REGINPUT" rev="51">
<attrib name="value" value="293"/></item> <attrib name="value" value="290"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="27"> <item name="NumNodesOfType_Active_SINGLE" rev="51">
<attrib name="value" value="2377"/></item> <attrib name="value" value="2153"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="27"> <item name="NumNodesOfType_Vcc_CNTRLPIN" rev="51">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_GENERIC" rev="27"> <item name="NumNodesOfType_Vcc_GENERIC" rev="51">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="27">
<attrib name="value" value="143"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="27">
<attrib name="value" value="13"/></item> <attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="27"> <item name="NumNodesOfType_Vcc_HVCCOUT" rev="51">
<attrib name="value" value="99"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="51">
<attrib name="value" value="13"/></item> <attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="27"> <item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="51">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="27">
<attrib name="value" value="386"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="27">
<attrib name="value" value="13"/></item> <attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="27"> <item name="NumNodesOfType_Vcc_KVCCOUT" rev="51">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="51">
<attrib name="value" value="259"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="51">
<attrib name="value" value="13"/></item> <attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="27"> <item name="NumNodesOfType_Vcc_PINBOUNCE" rev="51">
<attrib name="value" value="399"/></item> <attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_REGINPUT" rev="27"> <item name="NumNodesOfType_Vcc_PINFEED" rev="51">
<attrib name="value" value="11"/></item> <attrib name="value" value="272"/></item>
</group> </group>
<group name="SiteStatistics"> <group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="27"> <item name="BUFG-BUFGMUX" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="2"/></item>
<item name="IOB-IOBM" rev="27"> <item name="IOB-IOBM" rev="51">
<attrib name="value" value="162"/></item> <attrib name="value" value="162"/></item>
<item name="IOB-IOBS" rev="27"> <item name="IOB-IOBS" rev="51">
<attrib name="value" value="165"/></item> <attrib name="value" value="165"/></item>
<item name="SLICEL-SLICEM" rev="27"> <item name="SLICEL-SLICEM" rev="51">
<attrib name="value" value="33"/></item> <attrib name="value" value="38"/></item>
<item name="SLICEX-SLICEL" rev="27"> <item name="SLICEX-SLICEL" rev="51">
<attrib name="value" value="61"/></item> <attrib name="value" value="68"/></item>
<item name="SLICEX-SLICEM" rev="27"> <item name="SLICEX-SLICEM" rev="51">
<attrib name="value" value="75"/></item> <attrib name="value" value="59"/></item>
</group> </group>
<group name="MiscellaneousStatistics"> <group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="26"> <item name="AGG_BONDED_IO" rev="50">
<attrib name="value" value="331"/></item> <attrib name="value" value="331"/></item>
<item name="AGG_IO" rev="26"> <item name="AGG_IO" rev="50">
<attrib name="value" value="331"/></item> <attrib name="value" value="331"/></item>
<item name="AGG_LOCED_IO" rev="26"> <item name="AGG_LOCED_IO" rev="50">
<attrib name="value" value="329"/></item> <attrib name="value" value="329"/></item>
<item name="AGG_SLICE" rev="26"> <item name="AGG_SLICE" rev="50">
<attrib name="value" value="383"/></item> <attrib name="value" value="353"/></item>
<item name="NUM_BONDED_IOB" rev="26"> <item name="NUM_BONDED_IOB" rev="50">
<attrib name="value" value="327"/></item> <attrib name="value" value="327"/></item>
<item name="NUM_BONDED_IOBM" rev="26"> <item name="NUM_BONDED_IOBM" rev="50">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="NUM_BONDED_IOBS" rev="26"> <item name="NUM_BONDED_IOBS" rev="50">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="NUM_BSFULL" rev="26"> <item name="NUM_BSFULL" rev="50">
<attrib name="value" value="596"/></item> <attrib name="value" value="548"/></item>
<item name="NUM_BSLUTONLY" rev="26"> <item name="NUM_BSLUTONLY" rev="50">
<attrib name="value" value="369"/></item> <attrib name="value" value="330"/></item>
<item name="NUM_BSREGONLY" rev="26"> <item name="NUM_BSREGONLY" rev="50">
<attrib name="value" value="172"/></item> <attrib name="value" value="163"/></item>
<item name="NUM_BSUSED" rev="26"> <item name="NUM_BSUSED" rev="50">
<attrib name="value" value="1137"/></item> <attrib name="value" value="1041"/></item>
<item name="NUM_BUFG" rev="26"> <item name="NUM_BUFG" rev="50">
<attrib name="value" value="4"/></item> <attrib name="value" value="2"/></item>
<item name="NUM_DPRAM_O5ANDO6" rev="26"> <item name="NUM_DPRAM_O5ANDO6" rev="50">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O6ONLY" rev="26"> <item name="NUM_DPRAM_O6ONLY" rev="50">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="NUM_LOCED_IOB" rev="26"> <item name="NUM_LOCED_IOB" rev="50">
<attrib name="value" value="325"/></item> <attrib name="value" value="325"/></item>
<item name="NUM_LOCED_IOBM" rev="26"> <item name="NUM_LOCED_IOBM" rev="50">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="NUM_LOCED_IOBS" rev="26"> <item name="NUM_LOCED_IOBS" rev="50">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="26"> <item name="NUM_LOGIC_O5ANDO6" rev="50">
<attrib name="value" value="168"/></item> <attrib name="value" value="146"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="26"> <item name="NUM_LOGIC_O5ONLY" rev="50">
<attrib name="value" value="187"/></item> <attrib name="value" value="83"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="26"> <item name="NUM_LOGIC_O6ONLY" rev="50">
<attrib name="value" value="579"/></item> <attrib name="value" value="622"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="26"> <item name="NUM_LUT_RT_DRIVES_CARRY4" rev="50">
<attrib name="value" value="10"/></item> <attrib name="value" value="5"/></item>
<item name="NUM_LUT_RT_DRIVES_FLOP" rev="26"> <item name="NUM_LUT_RT_DRIVES_FLOP" rev="50">
<attrib name="value" value="7"/></item> <attrib name="value" value="8"/></item>
<item name="NUM_LUT_RT_EXO5" rev="26"> <item name="NUM_LUT_RT_EXO5" rev="50">
<attrib name="value" value="7"/></item> <attrib name="value" value="8"/></item>
<item name="NUM_LUT_RT_EXO6" rev="26"> <item name="NUM_LUT_RT_EXO6" rev="50">
<attrib name="value" value="10"/></item> <attrib name="value" value="5"/></item>
<item name="NUM_LUT_RT_O5" rev="26"> <item name="NUM_LUT_RT_O5" rev="50">
<attrib name="value" value="7"/></item>
<item name="NUM_LUT_RT_O6" rev="26">
<attrib name="value" value="187"/></item>
<item name="NUM_SLICEL" rev="26">
<attrib name="value" value="88"/></item>
<item name="NUM_SLICEM" rev="26">
<attrib name="value" value="4"/></item>
<item name="NUM_SLICEX" rev="26">
<attrib name="value" value="291"/></item>
<item name="NUM_SLICE_CARRY4" rev="26">
<attrib name="value" value="60"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="26">
<attrib name="value" value="34"/></item>
<item name="NUM_SLICE_CYINIT" rev="26">
<attrib name="value" value="1343"/></item>
<item name="NUM_SLICE_F7MUX" rev="26">
<attrib name="value" value="28"/></item>
<item name="NUM_SLICE_FF" rev="26">
<attrib name="value" value="834"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="26">
<attrib name="value" value="142"/></item>
<item name="NUM_SRL_O6ONLY" rev="26">
<attrib name="value" value="6"/></item> <attrib name="value" value="6"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="26"> <item name="NUM_LUT_RT_O6" rev="50">
<attrib name="value" value="83"/></item>
<item name="NUM_SLICEL" rev="50">
<attrib name="value" value="59"/></item>
<item name="NUM_SLICEM" rev="50">
<attrib name="value" value="4"/></item>
<item name="NUM_SLICEX" rev="50">
<attrib name="value" value="290"/></item>
<item name="NUM_SLICE_CARRY4" rev="50">
<attrib name="value" value="35"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="50">
<attrib name="value" value="26"/></item>
<item name="NUM_SLICE_CYINIT" rev="50">
<attrib name="value" value="1126"/></item>
<item name="NUM_SLICE_F7MUX" rev="50">
<attrib name="value" value="24"/></item>
<item name="NUM_SLICE_FF" rev="50">
<attrib name="value" value="784"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="50">
<attrib name="value" value="118"/></item>
<item name="NUM_SRL_O5ANDO6" rev="50">
<attrib name="value" value="2"/></item>
<item name="NUM_SRL_O6ONLY" rev="50">
<attrib name="value" value="4"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="50">
<attrib name="value" value="76"/></item> <attrib name="value" value="76"/></item>
</group> </group>
</DesignStatistics> </DesignStatistics>
<DeviceUsage TimeStamp="Mon Dec 20 17:37:10 2010"><group name="SiteSummary"> <DeviceUsage TimeStamp="Thu Jan 06 13:58:26 2011"><group name="SiteSummary">
<item name="BUFG" rev="27"> <item name="BUFG" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="BUFG_BUFG" rev="27"> <item name="BUFG_BUFG" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="CARRY4" rev="27"> <item name="CARRY4" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="60"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="35"/></item>
<item name="FF_SR" rev="27"> <item name="FF_SR" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="73"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="84"/></item>
<item name="HARD0" rev="27"> <item name="HARD0" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="5"/></item>
<item name="IOB" rev="27"> <item name="HARD1" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="327"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="327"/></item>
<item name="IOBM" rev="27"> <item name="IOBM" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBM_OUTBUF" rev="27"> <item name="IOBM_OUTBUF" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBS" rev="27"> <item name="IOBS" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB_IMUX" rev="27"> <item name="IOB_IMUX" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="160"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="160"/></item>
<item name="IOB_INBUF" rev="27"> <item name="IOB_INBUF" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="160"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="160"/></item>
<item name="IOB_OUTBUF" rev="27"> <item name="IOB_OUTBUF" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="198"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="198"/></item>
<item name="LUT5" rev="27"> <item name="LUT5" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="369"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="243"/></item>
<item name="LUT6" rev="27"> <item name="LUT6" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="944"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="856"/></item>
<item name="LUT_OR_MEM5" rev="27"> <item name="LUT_OR_MEM5" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
<item name="LUT_OR_MEM6" rev="27"> <item name="LUT_OR_MEM6" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="NULLMUX" rev="27"> <item name="NULLMUX" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="PAD" rev="27"> <item name="PAD" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="331"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="331"/></item>
<item name="REG_SR" rev="27"> <item name="REG_SR" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="761"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="700"/></item>
<item name="SELMUX2_1" rev="27"> <item name="SELMUX2_1" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="28"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="24"/></item>
<item name="SLICEL" rev="27"> <item name="SLICEL" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="88"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="59"/></item>
<item name="SLICEM" rev="27"> <item name="SLICEM" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="SLICEX" rev="27"> <item name="SLICEX" rev="51">
<attrib name="total" value="1000000"/><attrib name="used" value="291"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="290"/></item>
</group> </group>
</DeviceUsage> </DeviceUsage>
<ReportConfigData TimeStamp="Mon Dec 20 17:37:10 2010"><group name="REG_SR"> <ReportConfigData TimeStamp="Thu Jan 06 13:58:26 2011"><group name="REG_SR">
<item name="CK" rev="27"> <item name="CK" rev="51">
<attrib name="CK" value="761"/><attrib name="CK_INV" value="0"/></item> <attrib name="CK" value="700"/><attrib name="CK_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="27"> <item name="LATCH_OR_FF" rev="51">
<attrib name="FF" value="761"/></item> <attrib name="FF" value="700"/></item>
<item name="SRINIT" rev="27"> <item name="SRINIT" rev="51">
<attrib name="SRINIT0" value="709"/><attrib name="SRINIT1" value="52"/></item> <attrib name="SRINIT0" value="674"/><attrib name="SRINIT1" value="26"/></item>
<item name="SYNC_ATTR" rev="27"> <item name="SYNC_ATTR" rev="51">
<attrib name="ASYNC" value="253"/><attrib name="SYNC" value="508"/></item> <attrib name="ASYNC" value="221"/><attrib name="SYNC" value="479"/></item>
</group> </group>
<group name="LUT_OR_MEM5"> <group name="LUT_OR_MEM5">
<item name="CLK" rev="27"> <item name="CLK" rev="51">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item> <attrib name="CLK" value="6"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="27"> <item name="LUT_OR_MEM" rev="51">
<attrib name="RAM" value="4"/></item> <attrib name="RAM" value="6"/></item>
<item name="RAMMODE" rev="27"> <item name="RAMMODE" rev="51">
<attrib name="DPRAM32" value="4"/></item> <attrib name="SRL16" value="2"/><attrib name="DPRAM32" value="4"/></item>
</group> </group>
<group name="LUT_OR_MEM6"> <group name="LUT_OR_MEM6">
<item name="CLK" rev="27"> <item name="CLK" rev="51">
<attrib name="CLK" value="14"/><attrib name="CLK_INV" value="0"/></item> <attrib name="CLK" value="14"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="27"> <item name="LUT_OR_MEM" rev="51">
<attrib name="RAM" value="14"/></item> <attrib name="RAM" value="14"/></item>
<item name="RAMMODE" rev="27"> <item name="RAMMODE" rev="51">
<attrib name="SRL16" value="6"/><attrib name="DPRAM32" value="4"/><attrib name="DPRAM64" value="4"/></item> <attrib name="SRL16" value="6"/><attrib name="DPRAM32" value="4"/><attrib name="DPRAM64" value="4"/></item>
</group> </group>
<group name="IOBM_OUTBUF"> <group name="IOBM_OUTBUF">
<item name="SUSPEND" rev="27"> <item name="SUSPEND" rev="51">
<attrib name="3STATE" value="2"/></item> <attrib name="3STATE" value="2"/></item>
</group> </group>
<group name="SLICEL"> <group name="SLICEL">
<item name="CLK" rev="27"> <item name="CLK" rev="51">
<attrib name="CLK" value="47"/><attrib name="CLK_INV" value="0"/></item> <attrib name="CLK" value="33"/><attrib name="CLK_INV" value="0"/></item>
</group> </group>
<group name="SLICEM"> <group name="SLICEM">
<item name="CLK" rev="27"> <item name="CLK" rev="51">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item> <attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item>
</group> </group>
<group name="IOB_OUTBUF"> <group name="IOB_OUTBUF">
<item name="DRIVEATTRBOX" rev="27"> <item name="DRIVEATTRBOX" rev="51">
<attrib name="12" value="167"/></item> <attrib name="12" value="167"/></item>
<item name="SLEW" rev="27"> <item name="SLEW" rev="51">
<attrib name="SLOW" value="167"/></item> <attrib name="SLOW" value="167"/></item>
<item name="SUSPEND" rev="27"> <item name="SUSPEND" rev="51">
<attrib name="3STATE" value="198"/></item> <attrib name="3STATE" value="198"/></item>
</group> </group>
<group name="SLICEX"> <group name="SLICEX">
<item name="CLK" rev="27"> <item name="CLK" rev="51">
<attrib name="CLK" value="190"/><attrib name="CLK_INV" value="0"/></item> <attrib name="CLK" value="198"/><attrib name="CLK_INV" value="0"/></item>
</group> </group>
<group name="IOB_INBUF"> <group name="IOB_INBUF">
<item name="DIFF_TERM" rev="27"> <item name="DIFF_TERM" rev="51">
<attrib name="TRUE" value="1"/></item> <attrib name="TRUE" value="1"/></item>
</group> </group>
<group name="FF_SR"> <group name="FF_SR">
<item name="CK" rev="27"> <item name="CK" rev="51">
<attrib name="CK" value="73"/><attrib name="CK_INV" value="0"/></item> <attrib name="CK" value="84"/><attrib name="CK_INV" value="0"/></item>
<item name="SRINIT" rev="27"> <item name="SRINIT" rev="51">
<attrib name="SRINIT0" value="62"/><attrib name="SRINIT1" value="11"/></item> <attrib name="SRINIT0" value="72"/><attrib name="SRINIT1" value="12"/></item>
<item name="SYNC_ATTR" rev="27"> <item name="SYNC_ATTR" rev="51">
<attrib name="ASYNC" value="45"/><attrib name="SYNC" value="28"/></item> <attrib name="ASYNC" value="49"/><attrib name="SYNC" value="35"/></item>
</group> </group>
</ReportConfigData> </ReportConfigData>
<ReportPinData TimeStamp="Mon Dec 20 17:37:10 2010"><group name="NULLMUX"> <ReportPinData TimeStamp="Thu Jan 06 13:58:26 2011"><group name="NULLMUX">
<item name="0" rev="27"> <item name="0" rev="51">
<attrib name="value" value="3"/></item> <attrib name="value" value="3"/></item>
<item name="OUT" rev="27"> <item name="OUT" rev="51">
<attrib name="value" value="3"/></item> <attrib name="value" value="3"/></item>
</group> </group>
<group name="REG_SR"> <group name="REG_SR">
<item name="CE" rev="27"> <item name="CE" rev="51">
<attrib name="value" value="434"/></item> <attrib name="value" value="374"/></item>
<item name="CK" rev="27"> <item name="CK" rev="51">
<attrib name="value" value="761"/></item> <attrib name="value" value="700"/></item>
<item name="D" rev="27"> <item name="D" rev="51">
<attrib name="value" value="761"/></item> <attrib name="value" value="700"/></item>
<item name="Q" rev="27"> <item name="Q" rev="51">
<attrib name="value" value="761"/></item> <attrib name="value" value="700"/></item>
<item name="SR" rev="27"> <item name="SR" rev="51">
<attrib name="value" value="509"/></item> <attrib name="value" value="480"/></item>
</group> </group>
<group name="LUT_OR_MEM5"> <group name="LUT_OR_MEM5">
<item name="A1" rev="27"> <item name="A1" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="6"/></item>
<item name="A2" rev="27"> <item name="A2" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="6"/></item>
<item name="A3" rev="27"> <item name="A3" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="6"/></item>
<item name="A4" rev="27"> <item name="A4" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="6"/></item>
<item name="A5" rev="27"> <item name="A5" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="6"/></item>
<item name="CLK" rev="27"> <item name="CLK" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="6"/></item>
<item name="DI1" rev="27"> <item name="DI1" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="6"/></item>
<item name="O5" rev="27"> <item name="O5" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="6"/></item>
<item name="WA1" rev="27"> <item name="WA1" rev="51">
<attrib name="value" value="4"/></item>
<item name="WA2" rev="27">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="WA3" rev="27"> <item name="WA2" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="WA4" rev="27"> <item name="WA3" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="WA5" rev="27"> <item name="WA4" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="WE" rev="27"> <item name="WA5" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="WE" rev="51">
<attrib name="value" value="6"/></item>
</group> </group>
<group name="LUT_OR_MEM6"> <group name="LUT_OR_MEM6">
<item name="A1" rev="27"> <item name="A1" rev="51">
<attrib name="value" value="14"/></item> <attrib name="value" value="14"/></item>
<item name="A2" rev="27"> <item name="A2" rev="51">
<attrib name="value" value="14"/></item> <attrib name="value" value="14"/></item>
<item name="A3" rev="27"> <item name="A3" rev="51">
<attrib name="value" value="14"/></item> <attrib name="value" value="14"/></item>
<item name="A4" rev="27"> <item name="A4" rev="51">
<attrib name="value" value="14"/></item> <attrib name="value" value="14"/></item>
<item name="A5" rev="27"> <item name="A5" rev="51">
<attrib name="value" value="14"/></item> <attrib name="value" value="14"/></item>
<item name="A6" rev="27"> <item name="A6" rev="51">
<attrib name="value" value="14"/></item> <attrib name="value" value="14"/></item>
<item name="CLK" rev="27"> <item name="CLK" rev="51">
<attrib name="value" value="14"/></item> <attrib name="value" value="14"/></item>
<item name="DI1" rev="27"> <item name="DI1" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="DI2" rev="27"> <item name="DI2" rev="51">
<attrib name="value" value="10"/></item> <attrib name="value" value="10"/></item>
<item name="O6" rev="27"> <item name="O6" rev="51">
<attrib name="value" value="11"/></item> <attrib name="value" value="11"/></item>
<item name="WA1" rev="27"> <item name="WA1" rev="51">
<attrib name="value" value="8"/></item> <attrib name="value" value="8"/></item>
<item name="WA2" rev="27"> <item name="WA2" rev="51">
<attrib name="value" value="8"/></item> <attrib name="value" value="8"/></item>
<item name="WA3" rev="27"> <item name="WA3" rev="51">
<attrib name="value" value="8"/></item> <attrib name="value" value="8"/></item>
<item name="WA4" rev="27"> <item name="WA4" rev="51">
<attrib name="value" value="8"/></item> <attrib name="value" value="8"/></item>
<item name="WA5" rev="27"> <item name="WA5" rev="51">
<attrib name="value" value="8"/></item> <attrib name="value" value="8"/></item>
<item name="WA6" rev="27"> <item name="WA6" rev="51">
<attrib name="value" value="8"/></item> <attrib name="value" value="8"/></item>
<item name="WE" rev="27"> <item name="WE" rev="51">
<attrib name="value" value="14"/></item> <attrib name="value" value="14"/></item>
</group> </group>
<group name="IOBM_OUTBUF"> <group name="IOBM_OUTBUF">
<item name="IN" rev="27"> <item name="IN" rev="51">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="OUT" rev="27"> <item name="OUT" rev="51">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="OUTN" rev="27"> <item name="OUTN" rev="51">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
</group> </group>
<group name="SLICEL"> <group name="SLICEL">
<item name="A" rev="27"> <item name="A" rev="51">
<attrib name="value" value="13"/></item>
<item name="A1" rev="27">
<attrib name="value" value="11"/></item>
<item name="A2" rev="27">
<attrib name="value" value="15"/></item>
<item name="A3" rev="27">
<attrib name="value" value="19"/></item>
<item name="A4" rev="27">
<attrib name="value" value="61"/></item>
<item name="A5" rev="27">
<attrib name="value" value="33"/></item>
<item name="A6" rev="27">
<attrib name="value" value="74"/></item>
<item name="AMUX" rev="27">
<attrib name="value" value="19"/></item>
<item name="AQ" rev="27">
<attrib name="value" value="47"/></item>
<item name="AX" rev="27">
<attrib name="value" value="9"/></item> <attrib name="value" value="9"/></item>
<item name="B" rev="27"> <item name="A1" rev="51">
<attrib name="value" value="11"/></item>
<item name="B1" rev="27">
<attrib name="value" value="10"/></item>
<item name="B2" rev="27">
<attrib name="value" value="12"/></item>
<item name="B3" rev="27">
<attrib name="value" value="14"/></item>
<item name="B4" rev="27">
<attrib name="value" value="58"/></item>
<item name="B5" rev="27">
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<item name="O1" rev="27"> <item name="O1" rev="51">
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<item name="O2" rev="27"> <item name="O2" rev="51">
<attrib name="value" value="54"/></item> <attrib name="value" value="30"/></item>
<item name="O3" rev="27"> <item name="O3" rev="51">
<attrib name="value" value="51"/></item> <attrib name="value" value="29"/></item>
<item name="S0" rev="27"> <item name="S0" rev="51">
<attrib name="value" value="60"/></item> <attrib name="value" value="35"/></item>
<item name="S1" rev="27"> <item name="S1" rev="51">
<attrib name="value" value="59"/></item> <attrib name="value" value="35"/></item>
<item name="S2" rev="27"> <item name="S2" rev="51">
<attrib name="value" value="58"/></item> <attrib name="value" value="33"/></item>
<item name="S3" rev="27"> <item name="S3" rev="51">
<attrib name="value" value="54"/></item> <attrib name="value" value="31"/></item>
</group> </group>
<group name="IOBS"> <group name="IOBS">
<item name="DIFFO_IN" rev="27"> <item name="DIFFO_IN" rev="51">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="PAD" rev="27"> <item name="PAD" rev="51">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
</group> </group>
<group name="LUT5"> <group name="LUT5">
<item name="A1" rev="27"> <item name="A1" rev="51">
<attrib name="value" value="46"/></item> <attrib name="value" value="23"/></item>
<item name="A2" rev="27"> <item name="A2" rev="51">
<attrib name="value" value="48"/></item> <attrib name="value" value="27"/></item>
<item name="A3" rev="27"> <item name="A3" rev="51">
<attrib name="value" value="126"/></item> <attrib name="value" value="98"/></item>
<item name="A4" rev="27"> <item name="A4" rev="51">
<attrib name="value" value="131"/></item> <attrib name="value" value="101"/></item>
<item name="A5" rev="27"> <item name="A5" rev="51">
<attrib name="value" value="65"/></item> <attrib name="value" value="56"/></item>
<item name="O5" rev="27"> <item name="O5" rev="51">
<attrib name="value" value="369"/></item> <attrib name="value" value="243"/></item>
</group> </group>
<group name="LUT6"> <group name="LUT6">
<item name="A1" rev="27"> <item name="A1" rev="51">
<attrib name="value" value="302"/></item> <attrib name="value" value="286"/></item>
<item name="A2" rev="27"> <item name="A2" rev="51">
<attrib name="value" value="472"/></item> <attrib name="value" value="409"/></item>
<item name="A3" rev="27"> <item name="A3" rev="51">
<attrib name="value" value="572"/></item> <attrib name="value" value="525"/></item>
<item name="A4" rev="27"> <item name="A4" rev="51">
<attrib name="value" value="870"/></item> <attrib name="value" value="745"/></item>
<item name="A5" rev="27"> <item name="A5" rev="51">
<attrib name="value" value="755"/></item> <attrib name="value" value="770"/></item>
<item name="A6" rev="27"> <item name="A6" rev="51">
<attrib name="value" value="930"/></item> <attrib name="value" value="848"/></item>
<item name="O6" rev="27"> <item name="O6" rev="51">
<attrib name="value" value="944"/></item> <attrib name="value" value="856"/></item>
</group> </group>
<group name="SELMUX2_1"> <group name="SELMUX2_1">
<item name="0" rev="27"> <item name="0" rev="51">
<attrib name="value" value="28"/></item> <attrib name="value" value="24"/></item>
<item name="1" rev="27"> <item name="1" rev="51">
<attrib name="value" value="28"/></item> <attrib name="value" value="24"/></item>
<item name="OUT" rev="27"> <item name="OUT" rev="51">
<attrib name="value" value="28"/></item> <attrib name="value" value="24"/></item>
<item name="S0" rev="27"> <item name="S0" rev="51">
<attrib name="value" value="28"/></item> <attrib name="value" value="24"/></item>
</group> </group>
<group name="IOB_IMUX"> <group name="IOB_IMUX">
<item name="I" rev="27"> <item name="I" rev="51">
<attrib name="value" value="160"/></item> <attrib name="value" value="160"/></item>
<item name="OUT" rev="27"> <item name="OUT" rev="51">
<attrib name="value" value="160"/></item> <attrib name="value" value="160"/></item>
</group> </group>
<group name="IOB"> <group name="IOB">
<item name="DIFFI_IN" rev="27"> <item name="DIFFI_IN" rev="51">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="I" rev="27"> <item name="I" rev="51">
<attrib name="value" value="160"/></item> <attrib name="value" value="160"/></item>
<item name="O" rev="27"> <item name="O" rev="51">
<attrib name="value" value="198"/></item> <attrib name="value" value="198"/></item>
<item name="PAD" rev="27"> <item name="PAD" rev="51">
<attrib name="value" value="327"/></item> <attrib name="value" value="327"/></item>
<item name="PADOUT" rev="27"> <item name="PADOUT" rev="51">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="T" rev="27"> <item name="T" rev="51">
<attrib name="value" value="44"/></item> <attrib name="value" value="42"/></item>
</group> </group>
<group name="HARD0"> <group name="HARD0">
<item name="0" rev="27"> <item name="0" rev="51">
<attrib name="value" value="12"/></item> <attrib name="value" value="5"/></item>
</group>
<group name="HARD1">
<item name="1" rev="51">
<attrib name="value" value="2"/></item>
</group> </group>
<group name="FF_SR"> <group name="FF_SR">
<item name="CE" rev="27"> <item name="CE" rev="51">
<attrib name="value" value="36"/></item> <attrib name="value" value="41"/></item>
<item name="CK" rev="27"> <item name="CK" rev="51">
<attrib name="value" value="73"/></item> <attrib name="value" value="84"/></item>
<item name="D" rev="27"> <item name="D" rev="51">
<attrib name="value" value="73"/></item> <attrib name="value" value="84"/></item>
<item name="Q" rev="27"> <item name="Q" rev="51">
<attrib name="value" value="73"/></item> <attrib name="value" value="84"/></item>
<item name="SR" rev="27"> <item name="SR" rev="51">
<attrib name="value" value="28"/></item> <attrib name="value" value="35"/></item>
</group> </group>
<group name="BUFG"> <group name="BUFG">
<item name="I0" rev="27"> <item name="I0" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="2"/></item>
<item name="O" rev="27"> <item name="O" rev="51">
<attrib name="value" value="4"/></item> <attrib name="value" value="2"/></item>
</group> </group>
</ReportPinData> </ReportPinData>
<CmdHistory> <CmdHistory>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_xst.xrpt
View file @ cb70c6e4
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Mon Dec 20 17:22:46 2010"> <application stringID="Xst" timeStamp="Thu Jan 06 13:55:49 2011">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
...@@ -104,83 +104,80 @@ ...@@ -104,83 +104,80 @@
</section> </section>
<section stringID="XST_HDL_SYNTHESIS_REPORT"> <section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="1"></item> <item dataType="int" stringID="XST_RAMS" value="1"></item>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="14"> <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="9">
<item dataType="int" stringID="XST_16BIT_ADDER" value="2"/> <item dataType="int" stringID="XST_16BIT_ADDER" value="2"/>
<item dataType="int" stringID="XST_3BIT_ADDER" value="2"/> <item dataType="int" stringID="XST_3BIT_ADDER" value="2"/>
</item> </item>
<item dataType="int" stringID="XST_REGISTERS" value="114"> <item dataType="int" stringID="XST_REGISTERS" value="107">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="71"/> <item dataType="int" stringID="XST_1BIT_REGISTER" value="69"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="2"/> <item dataType="int" stringID="XST_16BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="4"/> <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_22BIT_REGISTER" value="1"/> <item dataType="int" stringID="XST_22BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="4"/> <item dataType="int" stringID="XST_3BIT_REGISTER" value="8"/>
<item dataType="int" stringID="XST_32BIT_REGISTER" value="15"/> <item dataType="int" stringID="XST_30BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="4"/> <item dataType="int" stringID="XST_32BIT_REGISTER" value="16"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_7BIT_REGISTER" value="1"/> <item dataType="int" stringID="XST_7BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="3"/> <item dataType="int" stringID="XST_8BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_9BIT_REGISTER" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_COMPARATORS" value="9"> <item dataType="int" stringID="XST_COMPARATORS" value="9">
<item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="1"/> <item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="1"/>
<item dataType="int" stringID="XST_3BIT_COMPARATOR_EQUAL" value="4"/> <item dataType="int" stringID="XST_3BIT_COMPARATOR_EQUAL" value="4"/>
</item> </item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="86"> <item dataType="int" stringID="XST_MULTIPLEXERS" value="76">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="44"/> <item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="34"/>
<item dataType="int" stringID="XST_1BIT_4TO1_MULTIPLEXER" value="2"/> <item dataType="int" stringID="XST_1BIT_4TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="8"/> <item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="8"/>
<item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="20"/> <item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="21"/>
<item dataType="int" stringID="XST_32BIT_4TO1_MULTIPLEXER" value="3"/> <item dataType="int" stringID="XST_32BIT_4TO1_MULTIPLEXER" value="3"/>
<item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="1"/> <item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_7BIT_2TO1_MULTIPLEXER" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_TRISTATES" value="64"> <item dataType="int" stringID="XST_TRISTATES" value="64">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="64"/> <item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="64"/>
</item> </item>
<item dataType="int" stringID="XST_FSMS" value="2"/> <item dataType="int" stringID="XST_FSMS" value="2"/>
<item dataType="int" stringID="XST_XORS" value="5"> <item dataType="int" stringID="XST_XORS" value="3">
<item dataType="int" stringID="XST_1BIT_XOR2" value="3"/> <item dataType="int" stringID="XST_1BIT_XOR2" value="1"/>
<item dataType="int" stringID="XST_1BIT_XOR6" value="2"/> <item dataType="int" stringID="XST_1BIT_XOR6" value="2"/>
</item> </item>
</section> </section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT"> <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="1"></item> <item dataType="int" stringID="XST_RAMS" value="1"></item>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="5"> <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4">
<item dataType="int" stringID="XST_16BIT_ADDER" value="1"/> <item dataType="int" stringID="XST_16BIT_ADDER" value="1"/>
<item dataType="int" stringID="XST_3BIT_ADDER" value="2"/> <item dataType="int" stringID="XST_3BIT_ADDER" value="2"/>
</item> </item>
<item dataType="int" stringID="XST_COUNTERS" value="11"> <item dataType="int" stringID="XST_COUNTERS" value="7">
<item dataType="int" stringID="XST_3BIT_UP_COUNTER" value="2"/> <item dataType="int" stringID="XST_3BIT_UP_COUNTER" value="2"/>
<item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_REGISTERS" value="689"> <item dataType="int" stringID="XST_REGISTERS" value="709">
<item dataType="int" stringID="XST_FLIPFLOPS" value="689"/> <item dataType="int" stringID="XST_FLIPFLOPS" value="709"/>
</item> </item>
<item dataType="int" stringID="XST_COMPARATORS" value="9"> <item dataType="int" stringID="XST_COMPARATORS" value="9">
<item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="1"/> <item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="1"/>
<item dataType="int" stringID="XST_3BIT_COMPARATOR_EQUAL" value="4"/> <item dataType="int" stringID="XST_3BIT_COMPARATOR_EQUAL" value="4"/>
</item> </item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="116"> <item dataType="int" stringID="XST_MULTIPLEXERS" value="106">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="44"/> <item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="34"/>
<item dataType="int" stringID="XST_1BIT_4TO1_MULTIPLEXER" value="34"/> <item dataType="int" stringID="XST_1BIT_4TO1_MULTIPLEXER" value="33"/>
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="8"/> <item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="8"/>
<item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="20"/> <item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="21"/>
<item dataType="int" stringID="XST_32BIT_4TO1_MULTIPLEXER" value="2"/> <item dataType="int" stringID="XST_32BIT_4TO1_MULTIPLEXER" value="2"/>
<item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="1"/> <item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_7BIT_2TO1_MULTIPLEXER" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_FSMS" value="2"/> <item dataType="int" stringID="XST_FSMS" value="2"/>
<item dataType="int" stringID="XST_XORS" value="5"> <item dataType="int" stringID="XST_XORS" value="3">
<item dataType="int" stringID="XST_1BIT_XOR2" value="3"/> <item dataType="int" stringID="XST_1BIT_XOR2" value="1"/>
<item dataType="int" stringID="XST_1BIT_XOR6" value="2"/> <item dataType="int" stringID="XST_1BIT_XOR6" value="2"/>
</item> </item>
</section> </section>
<section stringID="XST_FINAL_REGISTER_REPORT"> <section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="828"> <item dataType="int" stringID="XST_REGISTERS" value="776">
<item dataType="int" stringID="XST_FLIPFLOPS" value="828"/> <item dataType="int" stringID="XST_FLIPFLOPS" value="776"/>
</item> </item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="6"> <item dataType="int" stringID="XST_SHIFT_REGISTERS" value="8">
<item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="2"/> <item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_3BIT_SHIFT_REGISTER" value="4"/> <item dataType="int" stringID="XST_3BIT_SHIFT_REGISTER" value="6"/>
</item> </item>
</section> </section>
<section stringID="XST_PARTITION_REPORT"> <section stringID="XST_PARTITION_REPORT">
...@@ -193,70 +190,70 @@ ...@@ -193,70 +190,70 @@
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SFpga.ngc"/> <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SFpga.ngc"/>
</section> </section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE"> <section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="1555"> <item dataType="int" stringID="XST_BELS" value="1236">
<item dataType="int" stringID="XST_GND" value="1"/> <item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="32"/> <item dataType="int" stringID="XST_INV" value="23"/>
<item dataType="int" stringID="XST_LUT1" value="197"/> <item dataType="int" stringID="XST_LUT1" value="86"/>
<item dataType="int" stringID="XST_LUT2" value="168"/> <item dataType="int" stringID="XST_LUT2" value="211"/>
<item dataType="int" stringID="XST_LUT3" value="130"/> <item dataType="int" stringID="XST_LUT3" value="149"/>
<item dataType="int" stringID="XST_LUT4" value="116"/> <item dataType="int" stringID="XST_LUT4" value="85"/>
<item dataType="int" stringID="XST_LUT5" value="148"/> <item dataType="int" stringID="XST_LUT5" value="123"/>
<item dataType="int" stringID="XST_LUT6" value="298"/> <item dataType="int" stringID="XST_LUT6" value="284"/>
<item dataType="int" stringID="XST_MUXCY" value="220"/> <item dataType="int" stringID="XST_MUXCY" value="128"/>
<item dataType="int" stringID="XST_MUXF7" value="28"/> <item dataType="int" stringID="XST_MUXF7" value="24"/>
<item dataType="int" stringID="XST_VCC" value="1"/> <item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="216"/> <item dataType="int" stringID="XST_XORCY" value="121"/>
</item> </item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="834"> <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="784">
<item dataType="int" stringID="XST_FD" value="195"/> <item dataType="int" stringID="XST_FD" value="165"/>
<item dataType="int" stringID="XST_FDE" value="102"/> <item dataType="int" stringID="XST_FDE" value="104"/>
<item dataType="int" stringID="XST_FDPE" value="1"/> <item dataType="int" stringID="XST_FDPE" value="1"/>
<item dataType="int" stringID="XST_FDR" value="135"/> <item dataType="int" stringID="XST_FDR" value="170"/>
<item dataType="int" stringID="XST_FDRE" value="342"/> <item dataType="int" stringID="XST_FDRE" value="310"/>
<item dataType="int" stringID="XST_FDS" value="26"/> <item dataType="int" stringID="XST_FDS" value="26"/>
<item dataType="int" stringID="XST_FDSE" value="33"/> <item dataType="int" stringID="XST_FDSE" value="8"/>
</item> </item>
<item dataType="int" stringID="XST_RAMS" value="3"> <item dataType="int" stringID="XST_RAMS" value="3">
<item dataType="int" stringID="XST_RAM16X1D" value="2"/> <item dataType="int" stringID="XST_RAM16X1D" value="2"/>
</item> </item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="6"> <item dataType="int" stringID="XST_SHIFT_REGISTERS" value="8">
<item dataType="int" stringID="XST_SRLC16E" value="6"/> <item dataType="int" stringID="XST_SRLC16E" value="8"/>
</item> </item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="4"> <item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="2"/> <item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/>
<item dataType="int" stringID="XST_BUFGP" value="2"/> <item dataType="int" stringID="XST_BUFGP" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="303"> <item dataType="int" stringID="XST_IO_BUFFERS" value="304">
<item dataType="int" stringID="XST_IBUF" value="76"/> <item dataType="int" stringID="XST_IBUF" value="77"/>
<item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="32"/> <item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="32"/>
<item dataType="int" stringID="XST_OBUF" value="152"/> <item dataType="int" stringID="XST_OBUF" value="154"/>
<item dataType="int" stringID="XST_OBUFT" value="32"/> <item dataType="int" stringID="XST_OBUFT" value="30"/>
</item> </item>
</section> </section>
</section> </section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY"> <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="6slx150tfgg676-3"/> <item stringID="XST_SELECTED_DEVICE" value="6slx150tfgg676-3"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="834"/> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="784"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="1103"/> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="977"/>
<item AVAILABLE="92152" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="1089"/> <item AVAILABLE="92152" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="961"/>
<item AVAILABLE="21680" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="14"/> <item AVAILABLE="21680" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="16"/>
<item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="6"/> <item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="8"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1319"/> <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1207"/>
<item AVAILABLE="1319" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="485"/> <item AVAILABLE="1207" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="423"/>
<item AVAILABLE="1319" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="216"/> <item AVAILABLE="1207" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="230"/>
<item AVAILABLE="1319" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="618"/> <item AVAILABLE="1207" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="554"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="34"/> <item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="25"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="365"/> <item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="365"/>
<item AVAILABLE="396" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="316"/> <item AVAILABLE="396" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="316"/>
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="4"/> <item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="2"/>
</section> </section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY"> <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section> </section>
<section stringID="XST_ERRORS_STATISTICS"> <section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="130"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="132"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="12"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="17"/>
</section> </section>
</application> </application>
......
trunk/firmware/XilinxISE/SystemFpga/SystemFpga.gise
View file @ cb70c6e4
...@@ -68,6 +68,7 @@ ...@@ -68,6 +68,7 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/> <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="sfpga.bgn" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="sfpga.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_BIN" xil_pn:name="sfpga.bin"/> <file xil_pn:fileType="FILE_BIN" xil_pn:name="sfpga.bin"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="sfpga.bit" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="sfpga.bit" xil_pn:subbranch="FPGAConfiguration"/>
...@@ -110,7 +111,7 @@ ...@@ -110,7 +111,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292862183" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292862165"> <transform xil_pn:end_ts="1294318567" xil_pn:in_ck="-394197636941444327" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1294318548">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -128,11 +129,11 @@ ...@@ -128,11 +129,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1292862908" xil_pn:in_ck="119863998498621" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4066557905353815859" xil_pn:start_ts="1292862908"> <transform xil_pn:end_ts="1294306442" xil_pn:in_ck="119863998498621" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4066557905353815859" xil_pn:start_ts="1294306442">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292862913" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292862908"> <transform xil_pn:end_ts="1294318589" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1294318567">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -142,12 +143,10 @@ ...@@ -142,12 +143,10 @@
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292862953" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292862913"> <transform xil_pn:end_ts="1294318632" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1294318589">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SFpga.pcf"/> <outfile xil_pn:name="SFpga.pcf"/>
<outfile xil_pn:name="SFpga_map.map"/> <outfile xil_pn:name="SFpga_map.map"/>
<outfile xil_pn:name="SFpga_map.mrp"/> <outfile xil_pn:name="SFpga_map.mrp"/>
...@@ -158,7 +157,7 @@ ...@@ -158,7 +157,7 @@
<outfile xil_pn:name="SFpga_usage.xml"/> <outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292863002" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292862953"> <transform xil_pn:end_ts="1294318678" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1294318632">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -173,7 +172,7 @@ ...@@ -173,7 +172,7 @@
<outfile xil_pn:name="SFpga_par.xrpt"/> <outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292863036" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1292863002"> <transform xil_pn:end_ts="1294318722" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1294318678">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -189,7 +188,7 @@ ...@@ -189,7 +188,7 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1292864265" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1292864264"> <transform xil_pn:end_ts="1294318860" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1294318858">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="sfpga.isc"/> <outfile xil_pn:name="sfpga.isc"/>
...@@ -197,6 +196,9 @@ ...@@ -197,6 +196,9 @@
<transform xil_pn:end_ts="1292863315" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1292863313"> <transform xil_pn:end_ts="1292863315" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1292863313">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1292422596" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_createIBISModel_spartan6" xil_pn:prop_ck="-6143094129183081966" xil_pn:start_ts="1292422570"> <transform xil_pn:end_ts="1292422596" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_createIBISModel_spartan6" xil_pn:prop_ck="-6143094129183081966" xil_pn:start_ts="1292422570">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
...@@ -208,13 +210,13 @@ ...@@ -208,13 +210,13 @@
<status xil_pn:value="InputRemoved"/> <status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/> <status xil_pn:value="OutputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1292862605" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1292862604"> <transform xil_pn:end_ts="1294307159" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1294307157">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
</transform> </transform>
<transform xil_pn:end_ts="1292863002" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292862990"> <transform xil_pn:end_ts="1294318678" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1294318666">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SFpga.twr"/> <outfile xil_pn:name="SFpga.twr"/>
...@@ -227,12 +229,11 @@ ...@@ -227,12 +229,11 @@
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SFpga_preroute.twr"/> <status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="SFpga_preroute.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292862688" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1292862688"> <transform xil_pn:end_ts="1294306272" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1294306272">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
......
trunk/firmware/XilinxISE/SystemFpga/SystemFpga.xise
View file @ cb70c6e4
...@@ -19,10 +19,6 @@ ...@@ -19,10 +19,6 @@
<association xil_pn:name="BehavioralSimulation"/> <association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/> <association xil_pn:name="Implementation"/>
</file> </file>
<file xil_pn:name="../../../hdl/design/VmeInterfaceWB.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../hdl/design/AddrDecoderWBSys.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../hdl/design/AddrDecoderWBSys.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/> <association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/> <association xil_pn:name="Implementation"/>
...@@ -62,6 +58,10 @@ ...@@ -62,6 +58,10 @@
<file xil_pn:name="SFpga.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="SFpga.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/> <association xil_pn:name="Implementation"/>
</file> </file>
<file xil_pn:name="../../../hdl/design/VmeToWishBone.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
</files> </files>
<properties> <properties>
......
trunk/firmware/XilinxISE/SystemFpga/_ngo/netlist.lst
View file @ cb70c6e4
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292862182 C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1294318566
OK OK
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/bitgen.xmsgs
View file @ cb70c6e4
...@@ -8,13 +8,7 @@ ...@@ -8,13 +8,7 @@
<msg type="warning" file="Bitgen" num="244" delta="old" >A StartupClk setting other than JtagClk is being used to generate a bitstream in IEEE1532 format. The IEEE1532 option implies that JTAG configuration will be used. Using a StartupClk setting other than JtagClk could prevent proper device startup. <msg type="warning" file="Bitgen" num="244" delta="old" >A StartupClk setting other than JtagClk is being used to generate a bitstream in IEEE1532 format. The IEEE1532 option implies that JTAG configuration will be used. Using a StartupClk setting other than JtagClk could prevent proper device startup.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">i_Core/WriteCycle</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. <msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">i_Core/i_VmeInterface/Stb_oq</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
...@@ -86,6 +80,9 @@ ...@@ -86,6 +80,9 @@
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeAm_ib6&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeAm_ib6&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeSysClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
...@@ -131,6 +128,9 @@ ...@@ -131,6 +128,9 @@
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VcTcXo_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRLoS_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRLoS_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/map.xmsgs
View file @ cb70c6e4
...@@ -5,15 +5,15 @@ ...@@ -5,15 +5,15 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">N452</arg> has no load. <msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">N504</arg> has no load.
</msg> </msg>
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">54</arg> more times for the following (max. 5 shown): <msg type="info" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">54</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">N454, <arg fmt="%s" index="3">N506,
VmeAm_ib6&lt;2&gt;_IBUF, VmeAm_ib6&lt;2&gt;_IBUF,
VmeAm_ib6&lt;1&gt;_IBUF, VmeAm_ib6&lt;1&gt;_IBUF,
VmeDs_inb2&lt;2&gt;_IBUF, Switch_ib2&lt;1&gt;_IBUF,
VmeDs_inb2&lt;1&gt;_IBUF</arg> Switch_ib2&lt;0&gt;_IBUF</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch. To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
</msg> </msg>
...@@ -131,25 +131,18 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please ...@@ -131,25 +131,18 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts) <msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg> </msg>
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp). <msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
</msg>
<msg type="info" file="Place" num="834" delta="old" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">331</arg> IOs, <arg fmt="%d" index="2">329</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg> <msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg> </msg>
<msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component &lt;<arg fmt="%s" index="1">VmeSysClk_ik</arg>&gt; is placed at site &lt;<arg fmt="%s" index="2">PAD550</arg>&gt;. The corresponding BUFG component &lt;<arg fmt="%s" index="3">VmeSysClk_ik_BUFGP/BUFG</arg>&gt; is placed at site &lt;<arg fmt="%s" index="4">BUFGMUX_X2Y10</arg>&gt;. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">VmeSysClk_ik.PAD</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. <msg type="info" file="Place" num="834" delta="new" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">331</arg> IOs, <arg fmt="%d" index="2">329</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
</msg> </msg>
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design. <msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">i_Core/WriteCycle</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. <msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">i_Core/i_VmeInterface/Stb_oq</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
...@@ -221,6 +214,9 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please ...@@ -221,6 +214,9 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeAm_ib6&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeAm_ib6&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeSysClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
...@@ -266,6 +262,9 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please ...@@ -266,6 +262,9 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VcTcXo_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRLoS_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRLoS_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/ngdbuild.xmsgs
View file @ cb70c6e4
...@@ -5,18 +5,27 @@ ...@@ -5,18 +5,27 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N452</arg>&apos; has no driver <msg type="warning" file="ConstraintSystem" num="137" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;VcTcXo_ik&quot; TNM_NET = VcTcXo_ik;&gt; [SFpga.ucf(701)]</arg>: No appropriate instances for the TNM constraint are driven by &quot;<arg fmt="%s" index="2">VcTcXo_ik</arg>&quot;.
</msg> </msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N454</arg>&apos; has no driver <msg type="warning" file="ConstraintSystem" num="137" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;VmeSysClk_ik&quot; TNM_NET = VmeSysClk_ik;&gt; [SFpga.ucf(702)]</arg>: No appropriate instances for the TNM constraint are driven by &quot;<arg fmt="%s" index="2">VmeSysClk_ik</arg>&quot;.
</msg> </msg>
<msg type="warning" file="ConstraintSystem" num="194" delta="old" >The <arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">VcTcXo_ik</arg>&apos;, does not directly or indirectly drive any flip-flops, latches and/or RAMs and is not actively used by any referencing constraint.
</msg>
<msg type="warning" file="ConstraintSystem" num="194" delta="old" >The <arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">VmeSysClk_ik</arg>&apos;, does not directly or indirectly drive any flip-flops, latches and/or RAMs and is not actively used by any referencing constraint.
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;1&gt;</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;1&gt;</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;0&gt;</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;0&gt;</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">TempIdDQ_io</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;6&gt;</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;6&gt;</arg>&apos; has no legal driver
</msg> </msg>
...@@ -44,7 +53,10 @@ ...@@ -44,7 +53,10 @@
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgInit_io</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgInit_io</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">TempIdDQ_io</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="452" delta="new" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N504</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="new" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N506</arg>&apos; has no driver
</msg> </msg>
</messages> </messages>
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/par.xmsgs
View file @ cb70c6e4
...@@ -5,11 +5,7 @@ ...@@ -5,11 +5,7 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeDs_inb2&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeDs_inb2&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
...@@ -80,6 +76,9 @@ ...@@ -80,6 +76,9 @@
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeAm_ib6&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeAm_ib6&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeSysClk_ik_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
...@@ -125,6 +124,9 @@ ...@@ -125,6 +124,9 @@
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VcTcXo_ik_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">WRLoS_i_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">WRLoS_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
...@@ -155,11 +157,11 @@ ...@@ -155,11 +157,11 @@
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">50</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings. <msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">50</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg> </msg>
<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">50</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings. <msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">50</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg> </msg>
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/pn_parser.xmsgs
View file @ cb70c6e4
...@@ -8,5 +8,8 @@ ...@@ -8,5 +8,8 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/XilinxWrappers/SFpga.v\&quot; into library work</arg>
</msg>
</messages> </messages>
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/trce.xmsgs
View file @ cb70c6e4
...@@ -5,6 +5,8 @@ ...@@ -5,6 +5,8 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg> <msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg> <msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/xst.xmsgs
View file @ cb70c6e4
...@@ -14,31 +14,43 @@ ...@@ -14,31 +14,43 @@
<msg type="warning" file="HDLCompiler" num="572" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 250: Macro &lt;<arg fmt="%s" index="1">dly</arg>&gt; is redefined. <msg type="warning" file="HDLCompiler" num="572" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 250: Macro &lt;<arg fmt="%s" index="1">dly</arg>&gt; is redefined.
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="224" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to input <arg fmt="%s" index="1">AFpgaProgDone_io</arg> <msg type="warning" file="HDLCompiler" num="224" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 648: Assignment to input <arg fmt="%s" index="1">AFpgaProgDone_io</arg>
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 507: Port <arg fmt="%s" index="1">osc_clk</arg> is not connected to this instance <msg type="warning" file="HDLCompiler" num="1016" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 546: Port <arg fmt="%s" index="1">osc_clk</arg> is not connected to this instance
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 325: Assignment to <arg fmt="%s" index="1">DdrLDQS_io</arg> ignored, since the identifier is never used <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 323: Assignment to <arg fmt="%s" index="1">DdrLDQS_io</arg> ignored, since the identifier is never used
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 326: Assignment to <arg fmt="%s" index="1">DdrUDQS_io</arg> ignored, since the identifier is never used <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 324: Assignment to <arg fmt="%s" index="1">DdrUDQS_io</arg> ignored, since the identifier is never used
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 568: Assignment to <arg fmt="%s" index="1">GenericOutputReg3</arg> ignored, since the identifier is never used <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 370: Assignment to <arg fmt="%s" index="1">RstForLed</arg> ignored, since the identifier is never used
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to <arg fmt="%s" index="1">AFpgaProgDone_io</arg> ignored, since the identifier is never used <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 381: Assignment to <arg fmt="%s" index="1">DebugForLed1</arg> ignored, since the identifier is never used
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 268: Net &lt;<arg fmt="%s" index="1">GenericInputReg1[31]</arg>&gt; does not have a driver. <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 386: Assignment to <arg fmt="%s" index="1">DebugForLed2</arg> ignored, since the identifier is never used
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 273: Net &lt;<arg fmt="%s" index="1">SpiMiSo_b32[30]</arg>&gt; does not have a driver. <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 391: Assignment to <arg fmt="%s" index="1">DebugForLed3</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 396: Assignment to <arg fmt="%s" index="1">DebugForLed4</arg> ignored, since the identifier is never used
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 253: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">VmeDs_inb2</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit. <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to <arg fmt="%s" index="1">GenericOutputReg3</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 648: Assignment to <arg fmt="%s" index="1">AFpgaProgDone_io</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 268: Net &lt;<arg fmt="%s" index="1">GenericInputReg1[31]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 273: Net &lt;<arg fmt="%s" index="1">SpiMiSo_b32[30]</arg>&gt; does not have a driver.
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 439: Assignment to <arg fmt="%s" index="1">WRGBitOut_o</arg> ignored, since the identifier is never used <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 439: Assignment to <arg fmt="%s" index="1">WRGBitOut_o</arg> ignored, since the identifier is never used
...@@ -62,9 +74,6 @@ ...@@ -62,9 +74,6 @@
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 453: Assignment to <arg fmt="%s" index="1">Gbit4Sys2App_o</arg> ignored, since the identifier is never used <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 453: Assignment to <arg fmt="%s" index="1">Gbit4Sys2App_o</arg> ignored, since the identifier is never used
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 253: Net &lt;<arg fmt="%s" index="1">VmeDs_i</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 440: Net &lt;<arg fmt="%s" index="1">WRGbitIn_i</arg>&gt; does not have a driver. <msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 440: Net &lt;<arg fmt="%s" index="1">WRGbitIn_i</arg>&gt; does not have a driver.
</msg> </msg>
...@@ -95,7 +104,19 @@ ...@@ -95,7 +104,19 @@
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 455: Net &lt;<arg fmt="%s" index="1">Gbit34RefClk_ik</arg>&gt; does not have a driver. <msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 455: Net &lt;<arg fmt="%s" index="1">Gbit34RefClk_ik</arg>&gt; does not have a driver.
</msg> </msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;2:1&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. <msg type="warning" file="Xst" num="2972" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">367</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">i_ClearMonostable</arg>&gt; of block &lt;<arg fmt="%s" index="4">Monostable</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">SystemFpga</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">378</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">i_Debug1Monostable</arg>&gt; of block &lt;<arg fmt="%s" index="4">Monostable</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">SystemFpga</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">383</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">i_Debug2Monostable</arg>&gt; of block &lt;<arg fmt="%s" index="4">Monostable</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">SystemFpga</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">388</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">i_Debug3Monostable</arg>&gt; of block &lt;<arg fmt="%s" index="4">Monostable</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">SystemFpga</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">393</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">i_Debug4Monostable</arg>&gt; of block &lt;<arg fmt="%s" index="4">Monostable</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">SystemFpga</arg>&gt;. Underlying logic will be removed.
</msg> </msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/xilinxwrappers/sfpga.v</arg>&quot; line <arg fmt="%d" index="2">233</arg>: Output port &lt;<arg fmt="%s" index="3">WRGBitOut_o</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Core</arg>&gt; is unconnected or connected to loadless signal. <msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/xilinxwrappers/sfpga.v</arg>&quot; line <arg fmt="%d" index="2">233</arg>: Output port &lt;<arg fmt="%s" index="3">WRGBitOut_o</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Core</arg>&gt; is unconnected or connected to loadless signal.
...@@ -119,9 +140,6 @@ ...@@ -119,9 +140,6 @@
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/xilinxwrappers/sfpga.v</arg>&quot; line <arg fmt="%d" index="2">233</arg>: Output port &lt;<arg fmt="%s" index="3">Gbit4Sys2App_o</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Core</arg>&gt; is unconnected or connected to loadless signal. <msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/xilinxwrappers/sfpga.v</arg>&quot; line <arg fmt="%d" index="2">233</arg>: Output port &lt;<arg fmt="%s" index="3">Gbit4Sys2App_o</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Core</arg>&gt; is unconnected or connected to loadless signal.
</msg> </msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">VmeDs_i</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">WRGbitIn_i</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>. <msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">WRGbitIn_i</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg> </msg>
...@@ -158,6 +176,9 @@ ...@@ -158,6 +176,9 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg> </msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeSysClk_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeTck_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeTck_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg> </msg>
...@@ -170,6 +191,9 @@ ...@@ -170,6 +191,9 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeTms_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeTms_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg> </msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VcTcXo_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">AFpgaProgDone_io</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">AFpgaProgDone_io</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg> </msg>
...@@ -278,10 +302,25 @@ ...@@ -278,10 +302,25 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Gbit34RefClk_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Gbit34RefClk_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg> </msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">507</arg>: Output port &lt;<arg fmt="%s" index="3">osc_clk</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_InterruptManager</arg>&gt; is unconnected or connected to loadless signal. <msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">367</arg>: Output port &lt;<arg fmt="%s" index="3">SynchOutput_oq</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_ClearMonostable</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">378</arg>: Output port &lt;<arg fmt="%s" index="3">SynchOutput_oq</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Debug1Monostable</arg>&gt; is unconnected or connected to loadless signal.
</msg> </msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">555</arg>: Output port &lt;<arg fmt="%s" index="3">Reg3Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Generic4OutputRegs</arg>&gt; is unconnected or connected to loadless signal. <msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">383</arg>: Output port &lt;<arg fmt="%s" index="3">SynchOutput_oq</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Debug2Monostable</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">388</arg>: Output port &lt;<arg fmt="%s" index="3">SynchOutput_oq</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Debug3Monostable</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">393</arg>: Output port &lt;<arg fmt="%s" index="3">SynchOutput_oq</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Debug4Monostable</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">546</arg>: Output port &lt;<arg fmt="%s" index="3">osc_clk</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_InterruptManager</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">595</arg>: Output port &lt;<arg fmt="%s" index="3">Reg3Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Generic4OutputRegs</arg>&gt; is unconnected or connected to loadless signal.
</msg> </msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">GenericInputReg1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>. <msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">GenericInputReg1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
...@@ -329,34 +368,16 @@ ...@@ -329,34 +368,16 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Rst_irq</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Rst_irq</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg> </msg>
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">ds1_shr_0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">i_VmeInterface</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">ds2_shr_0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">i_VmeInterface</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">ds1_shr_1</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">i_VmeInterface</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">ds2_shr_1</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">i_VmeInterface</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="info" file="Xst" num="3031" delta="old" >HDL ADVISOR - The RAM &lt;<arg fmt="%s" index="1">Mram_int_fifo</arg>&gt; will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. <msg type="info" file="Xst" num="3031" delta="old" >HDL ADVISOR - The RAM &lt;<arg fmt="%s" index="1">Mram_int_fifo</arg>&gt; will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
</msg> </msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">ds1_shr_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">VmeInterfaceWB</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;ds2_shr_0&gt; </arg> <msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">CntrlShReg_b32_31</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">Slv2SerWB</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">ds1_shr_0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">VmeInterfaceWB</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">ds1_shr_1</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">VmeInterfaceWB</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg> </msg>
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">ds2_shr_1</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">VmeInterfaceWB</arg>&gt;. This FF/Latch will be trimmed during the optimization process. <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">Stb_oq</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">VmeToWishBone</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;Cyc_oq&gt; </arg>
</msg> </msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">CntrlShReg_b32_31</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">Slv2SerWB</arg>&gt;. This FF/Latch will be trimmed during the optimization process. <msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_AddressDecoderWB/StbGenericInputRegs_o</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg> </msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;. <msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
......
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport
View file @ cb70c6e4
<?xml version='1.0' encoding='UTF-8'?> <?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" > <report-views version="2.0" >
<header> <header>
<DateModified>2010-12-20T16:40:12</DateModified> <DateModified>2011-01-06T10:33:53</DateModified>
<ModuleName>SFpga</ModuleName> <ModuleName>SFpga</ModuleName>
<SummaryTimeStamp>2010-12-20T13:49:08</SummaryTimeStamp> <SummaryTimeStamp>2010-12-20T13:49:08</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath> <SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath>
......
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SystemFpga.projectmgr
View file @ cb70c6e4
...@@ -10,13 +10,13 @@ ...@@ -10,13 +10,13 @@
<ClosedNode>/ApplicationFpga C:|VFC_SVN|hdl|design|ApplicationFpga.v</ClosedNode> <ClosedNode>/ApplicationFpga C:|VFC_SVN|hdl|design|ApplicationFpga.v</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem>i_SpiMasterWB - SpiMasterWB (C:/VFC_SVN/hdl/design/SpiMasterWB.v)</SelectedItem> <SelectedItem>SFpga (C:/VFC_SVN/hdl/design/XilinxWrappers/SFpga.v)</SelectedItem>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000191000000020000000000000000000000000000000064ffffffff000000810000000000000002000001910000000100000000000000000000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000191000000020000000000000000000000000000000064ffffffff000000810000000000000002000001910000000100000000000000000000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>i_SpiMasterWB - SpiMasterWB (C:/VFC_SVN/hdl/design/SpiMasterWB.v)</CurrentItem> <CurrentItem>SFpga (C:/VFC_SVN/hdl/design/XilinxWrappers/SFpga.v)</CurrentItem>
</ItemView> </ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes> <ClosedNodes>
...@@ -57,7 +57,7 @@ ...@@ -57,7 +57,7 @@
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes> <ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion> <ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode> <ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
<ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode> <ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode> <ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode> <ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
...@@ -68,7 +68,7 @@ ...@@ -68,7 +68,7 @@
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000189000000010000000100000000000000000000000064ffffffff000000810000000000000001000001890000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem> <CurrentItem></CurrentItem>
</ItemView> </ItemView>
......
trunk/firmware/XilinxISE/SystemFpga/pa.fromNetlist.tcl
View file @ cb70c6e4
# PlanAhead Launch Script for Post-Synthesis pin planning, created by Project Navigator # PlanAhead Launch Script for Post-Synthesis pin planning, created by Project Navigator
create_project -name SystemFpga -dir "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/planAhead_run_1" -part xc6slx150tfgg676-3 create_project -name SystemFpga -dir "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/planAhead_run_2" -part xc6slx150tfgg676-3
set_property design_mode GateLvl [get_property srcset [current_run -impl]] set_property design_mode GateLvl [get_property srcset [current_run -impl]]
set_property edif_top_file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" [ get_property srcset [ current_run ] ] set_property edif_top_file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" [ get_property srcset [ current_run ] ]
add_files -norecurse { {C:/VFC_SVN/firmware/XilinxISE/SystemFpga} } add_files -norecurse { {C:/VFC_SVN/firmware/XilinxISE/SystemFpga} }
......
trunk/firmware/XilinxISE/SystemFpga/par_usage_statistics.html
View file @ cb70c6e4
<TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics"> <xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1527</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1382</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4741</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4464</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4741</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4464</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4348</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4129</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.5 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>15.1 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>14.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>21.9 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>21.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>27.6 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>26.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>30.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>29.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>30.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>29.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>30.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>29.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>30.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>29.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>30.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>29.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>30.7 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>29.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>14.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>18.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>9.5</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>11.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>6.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>12.2</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>11.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>13.4</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>7.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>15.9</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>8.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>8.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>4.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0653</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0783</xtag-par-property-value></TD></TR>
</xtag-section> </xtag-section>
</TABLE> </TABLE>
trunk/firmware/XilinxISE/SystemFpga/planAhead.ngc2edif.log
View file @ cb70c6e4
...@@ -141,3 +141,36 @@ Processing design ... ...@@ -141,3 +141,36 @@ Processing design ...
Writing EDIF netlist file SFpga.edif ... Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 75544 kilobytes ngc2edif: Total memory usage is 75544 kilobytes
Release 12.3 - ngc2edif M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 71476 kilobytes
Release 12.3 - ngc2edif M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 71156 kilobytes
Release 12.3 - ngc2edif M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 71476 kilobytes
trunk/firmware/XilinxISE/SystemFpga/sfpga.bgn
View file @ cb70c6e4
...@@ -5,7 +5,7 @@ C:\Xilinx\12.3\ISE_DS\ISE\. ...@@ -5,7 +5,7 @@ C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3 "SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Opened constraints file SFpga.pcf. Opened constraints file SFpga.pcf.
Mon Dec 20 17:36:48 2010 Thu Jan 06 13:58:04 2011
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
...@@ -126,13 +126,10 @@ There were 0 CONFIG constraint(s) processed from SFpga.pcf. ...@@ -126,13 +126,10 @@ There were 0 CONFIG constraint(s) processed from SFpga.pcf.
Running DRC. Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_Core/WriteCycle is WARNING:PhysDesignRules:372 - Gated clock. Clock net
sourced by a combinatorial pin. This is not good design practice. Use the CE i_Core/i_VmeInterface/Stb_oq is sourced by a combinatorial pin. This is not
pin to control the loading of data into the flip-flop. good design practice. Use the CE pin to control the loading of data into the
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The flip-flop.
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
...@@ -179,6 +176,8 @@ WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The ...@@ -179,6 +176,8 @@ WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeSysClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The
...@@ -209,6 +208,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is ...@@ -209,6 +208,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VcTcXo_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.drc
View file @ cb70c6e4
Release 12.3 Drc M.70d (nt64) Release 12.3 Drc M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 17:36:48 2010 Thu Jan 06 13:58:04 2011
drc -z SFpga.ncd SFpga.pcf drc -z SFpga.ncd SFpga.pcf
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_Core/WriteCycle is WARNING:PhysDesignRules:372 - Gated clock. Clock net
sourced by a combinatorial pin. This is not good design practice. Use the CE i_Core/i_VmeInterface/Stb_oq is sourced by a combinatorial pin. This is not
pin to control the loading of data into the flip-flop. good design practice. Use the CE pin to control the loading of data into the
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The flip-flop.
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
...@@ -58,6 +55,8 @@ WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The ...@@ -58,6 +55,8 @@ WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeSysClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The
...@@ -88,6 +87,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is ...@@ -88,6 +87,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VcTcXo_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design. signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.isc
View file @ cb70c6e4
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/sfpga.rbt
View file @ cb70c6e4
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html
View file @ cb70c6e4
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD> <TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">effa8437e76f45ca9db699794ac1987e</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">12</xtag-property></TD> <TD><xtag-property name="RandomID">effa8437e76f45ca9db699794ac1987e</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">24</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD> <TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">fgg676</xtag-property></TD> <TD><xtag-property name="TargetPackage">fgg676</xtag-property></TD>
</TR> </TR>
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD> <TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2010-12-20T17:37:11</xtag-property></TD> <TD><xtag-property name="Date Generated">2011-01-06T13:58:26</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD> <TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD> <TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR> </TR>
...@@ -67,11 +67,10 @@ ...@@ -67,11 +67,10 @@
<TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP> <TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="MacroStatistics"> <xtag-section name="MacroStatistics">
<TD> <TD>
<xtag-group><xtag-group-name name="Adders/Subtractors=5">Adders/Subtractors=5</xtag-group-name> <xtag-group><xtag-group-name name="Adders/Subtractors=4">Adders/Subtractors=4</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>12-bit adder=1</xtag-item1></LI> <LI><xtag-item1>12-bit adder=1</xtag-item1></LI>
<LI><xtag-item1>16-bit adder=1</xtag-item1></LI> <LI><xtag-item1>16-bit adder=1</xtag-item1></LI>
<LI><xtag-item1>22-bit adder=1</xtag-item1></LI>
<LI><xtag-item1>3-bit adder=2</xtag-item1></LI> <LI><xtag-item1>3-bit adder=2</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
...@@ -84,31 +83,30 @@ ...@@ -84,31 +83,30 @@
<LI><xtag-item1>8-bit comparator equal=1</xtag-item1></LI> <LI><xtag-item1>8-bit comparator equal=1</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="Counters=11">Counters=11</xtag-group-name> <xtag-group><xtag-group-name name="Counters=7">Counters=7</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>16-bit up counter=1</xtag-item1></LI> <LI><xtag-item1>16-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>23-bit up counter=3</xtag-item1></LI> <LI><xtag-item1>23-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>24-bit up counter=3</xtag-item1></LI> <LI><xtag-item1>24-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>3-bit up counter=2</xtag-item1></LI> <LI><xtag-item1>3-bit up counter=2</xtag-item1></LI>
<LI><xtag-item1>30-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>4-bit updown counter=1</xtag-item1></LI> <LI><xtag-item1>4-bit updown counter=1</xtag-item1></LI>
<LI><xtag-item1>9-bit up counter=1</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="FSMs=2">FSMs=2</xtag-group-name> <xtag-group><xtag-group-name name="FSMs=2">FSMs=2</xtag-group-name>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="Multiplexers=116">Multiplexers=116</xtag-group-name> <xtag-group><xtag-group-name name="Multiplexers=106">Multiplexers=106</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>1-bit 2-to-1 multiplexer=44</xtag-item1></LI> <LI><xtag-item1>1-bit 2-to-1 multiplexer=34</xtag-item1></LI>
<LI><xtag-item1>1-bit 32-to-1 multiplexer=1</xtag-item1></LI> <LI><xtag-item1>1-bit 32-to-1 multiplexer=1</xtag-item1></LI>
<LI><xtag-item1>1-bit 4-to-1 multiplexer=34</xtag-item1></LI> <LI><xtag-item1>1-bit 4-to-1 multiplexer=33</xtag-item1></LI>
<LI><xtag-item1>12-bit 2-to-1 multiplexer=2</xtag-item1></LI> <LI><xtag-item1>12-bit 2-to-1 multiplexer=2</xtag-item1></LI>
<LI><xtag-item1>16-bit 2-to-1 multiplexer=8</xtag-item1></LI> <LI><xtag-item1>16-bit 2-to-1 multiplexer=8</xtag-item1></LI>
<LI><xtag-item1>22-bit 2-to-1 multiplexer=2</xtag-item1></LI> <LI><xtag-item1>22-bit 2-to-1 multiplexer=3</xtag-item1></LI>
<LI><xtag-item1>32-bit 2-to-1 multiplexer=20</xtag-item1></LI> <LI><xtag-item1>32-bit 2-to-1 multiplexer=21</xtag-item1></LI>
<LI><xtag-item1>32-bit 4-to-1 multiplexer=2</xtag-item1></LI> <LI><xtag-item1>32-bit 4-to-1 multiplexer=2</xtag-item1></LI>
<LI><xtag-item1>32-bit 7-to-1 multiplexer=1</xtag-item1></LI> <LI><xtag-item1>32-bit 7-to-1 multiplexer=1</xtag-item1></LI>
<LI><xtag-item1>5-bit 2-to-1 multiplexer=1</xtag-item1></LI> <LI><xtag-item1>5-bit 2-to-1 multiplexer=1</xtag-item1></LI>
<LI><xtag-item1>7-bit 2-to-1 multiplexer=1</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="RAMs=1">RAMs=1</xtag-group-name> <xtag-group><xtag-group-name name="RAMs=1">RAMs=1</xtag-group-name>
...@@ -116,14 +114,14 @@ ...@@ -116,14 +114,14 @@
<LI><xtag-item1>8x8-bit dual-port distributed RAM=1</xtag-item1></LI> <LI><xtag-item1>8x8-bit dual-port distributed RAM=1</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="Registers=689">Registers=689</xtag-group-name> <xtag-group><xtag-group-name name="Registers=709">Registers=709</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>Flip-Flops=689</xtag-item1></LI> <LI><xtag-item1>Flip-Flops=709</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="Xors=5">Xors=5</xtag-group-name> <xtag-group><xtag-group-name name="Xors=3">Xors=3</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>1-bit xor2=3</xtag-item1></LI> <LI><xtag-item1>1-bit xor2=1</xtag-item1></LI>
<LI><xtag-item1>1-bit xor6=2</xtag-item1></LI> <LI><xtag-item1>1-bit xor6=2</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
...@@ -136,39 +134,40 @@ ...@@ -136,39 +134,40 @@
<LI><xtag-item1>AGG_BONDED_IO=331</xtag-item1></LI> <LI><xtag-item1>AGG_BONDED_IO=331</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=331</xtag-item1></LI> <LI><xtag-item1>AGG_IO=331</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=329</xtag-item1></LI> <LI><xtag-item1>AGG_LOCED_IO=329</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=383</xtag-item1></LI> <LI><xtag-item1>AGG_SLICE=353</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=327</xtag-item1></LI> <LI><xtag-item1>NUM_BONDED_IOB=327</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBM=2</xtag-item1></LI> <LI><xtag-item1>NUM_BONDED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBS=2</xtag-item1></LI> <LI><xtag-item1>NUM_BONDED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=596</xtag-item1></LI> <LI><xtag-item1>NUM_BSFULL=548</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=369</xtag-item1></LI> <LI><xtag-item1>NUM_BSLUTONLY=330</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=172</xtag-item1></LI> <LI><xtag-item1>NUM_BSREGONLY=163</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=1137</xtag-item1></LI> <LI><xtag-item1>NUM_BSUSED=1041</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=4</xtag-item1></LI> <LI><xtag-item1>NUM_BUFG=2</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O5ANDO6=4</xtag-item1></LI> <LI><xtag-item1>NUM_DPRAM_O5ANDO6=4</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O6ONLY=4</xtag-item1></LI> <LI><xtag-item1>NUM_DPRAM_O6ONLY=4</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOB=325</xtag-item1></LI> <LI><xtag-item1>NUM_LOCED_IOB=325</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOBM=2</xtag-item1></LI> <LI><xtag-item1>NUM_LOCED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOBS=2</xtag-item1></LI> <LI><xtag-item1>NUM_LOCED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=168</xtag-item1></LI> <LI><xtag-item1>NUM_LOGIC_O5ANDO6=146</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=187</xtag-item1></LI> <LI><xtag-item1>NUM_LOGIC_O5ONLY=83</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=579</xtag-item1></LI> <LI><xtag-item1>NUM_LOGIC_O6ONLY=622</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=10</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=5</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=7</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=8</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO5=7</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_EXO5=8</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO6=10</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_EXO6=5</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O5=7</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_O5=6</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=187</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_O6=83</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=88</xtag-item1></LI> <LI><xtag-item1>NUM_SLICEL=59</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEM=4</xtag-item1></LI> <LI><xtag-item1>NUM_SLICEM=4</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=291</xtag-item1></LI> <LI><xtag-item1>NUM_SLICEX=290</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=60</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_CARRY4=35</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=34</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_CONTROLSET=26</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=1343</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_CYINIT=1126</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_F7MUX=28</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_F7MUX=24</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=834</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_FF=784</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=142</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=118</xtag-item1></LI>
<LI><xtag-item1>NUM_SRL_O6ONLY=6</xtag-item1></LI> <LI><xtag-item1>NUM_SRL_O5ANDO6=2</xtag-item1></LI>
<LI><xtag-item1>NUM_SRL_O6ONLY=4</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=76</xtag-item1></LI> <LI><xtag-item1>NUM_UNUSABLE_FF_BELS=76</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
...@@ -176,53 +175,52 @@ ...@@ -176,53 +175,52 @@
<TD> <TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name> <xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>NumNets_Active=1908</xtag-item1></LI> <LI><xtag-item1>NumNets_Active=1763</xtag-item1></LI>
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI> <LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI> <LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=25</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=29</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=200</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=224</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=4</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=20</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=14</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=241</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_CLKPIN=235</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=26</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=14</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=287</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=270</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=2086</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_DOUBLE=1968</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=354</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_GENERIC=353</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=181</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_GLOBAL=136</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=60</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_INPUT=38</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=243</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=242</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=243</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=242</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3723</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3496</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1593</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1466</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1471</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1307</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=137</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_PADINPUT=135</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=114</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=114</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=839</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=773</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=4266</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_PINFEED=4025</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=5699</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_QUAD=5651</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=293</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_REGINPUT=290</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=2377</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_SINGLE=2153</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=2</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_GENERIC=13</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_GENERIC=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=143</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=99</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBIN2OUT=13</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_IOBIN2OUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBOUTPUT=13</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_IOBOUTPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=6</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=386</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=259</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PADINPUT=13</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_PADINPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=13</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=399</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=272</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_REGINPUT=11</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name> <xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>BUFG-BUFGMUX=4</xtag-item1></LI> <LI><xtag-item1>BUFG-BUFGMUX=2</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBM=162</xtag-item1></LI> <LI><xtag-item1>IOB-IOBM=162</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=165</xtag-item1></LI> <LI><xtag-item1>IOB-IOBS=165</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=33</xtag-item1></LI> <LI><xtag-item1>SLICEL-SLICEM=38</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=61</xtag-item1></LI> <LI><xtag-item1>SLICEX-SLICEL=68</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=75</xtag-item1></LI> <LI><xtag-item1>SLICEX-SLICEM=59</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
</TD> </TD>
...@@ -231,11 +229,12 @@ ...@@ -231,11 +229,12 @@
<TD> <TD>
<xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name> <xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name>
<UL> <UL>
<LI><xtag-item2>BUFG=4</xtag-item2></LI> <LI><xtag-item2>BUFG=2</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=4</xtag-item2></LI> <LI><xtag-item2>BUFG_BUFG=2</xtag-item2></LI>
<LI><xtag-item2>CARRY4=60</xtag-item2></LI> <LI><xtag-item2>CARRY4=35</xtag-item2></LI>
<LI><xtag-item2>FF_SR=73</xtag-item2></LI> <LI><xtag-item2>FF_SR=84</xtag-item2></LI>
<LI><xtag-item2>HARD0=12</xtag-item2></LI> <LI><xtag-item2>HARD0=5</xtag-item2></LI>
<LI><xtag-item2>HARD1=2</xtag-item2></LI>
<LI><xtag-item2>IOB=327</xtag-item2></LI> <LI><xtag-item2>IOB=327</xtag-item2></LI>
<LI><xtag-item2>IOBM=2</xtag-item2></LI> <LI><xtag-item2>IOBM=2</xtag-item2></LI>
<LI><xtag-item2>IOBM_OUTBUF=2</xtag-item2></LI> <LI><xtag-item2>IOBM_OUTBUF=2</xtag-item2></LI>
...@@ -243,17 +242,17 @@ ...@@ -243,17 +242,17 @@
<LI><xtag-item2>IOB_IMUX=160</xtag-item2></LI> <LI><xtag-item2>IOB_IMUX=160</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=160</xtag-item2></LI> <LI><xtag-item2>IOB_INBUF=160</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=198</xtag-item2></LI> <LI><xtag-item2>IOB_OUTBUF=198</xtag-item2></LI>
<LI><xtag-item2>LUT5=369</xtag-item2></LI> <LI><xtag-item2>LUT5=243</xtag-item2></LI>
<LI><xtag-item2>LUT6=944</xtag-item2></LI> <LI><xtag-item2>LUT6=856</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM5=4</xtag-item2></LI> <LI><xtag-item2>LUT_OR_MEM5=6</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM6=14</xtag-item2></LI> <LI><xtag-item2>LUT_OR_MEM6=14</xtag-item2></LI>
<LI><xtag-item2>NULLMUX=3</xtag-item2></LI> <LI><xtag-item2>NULLMUX=3</xtag-item2></LI>
<LI><xtag-item2>PAD=331</xtag-item2></LI> <LI><xtag-item2>PAD=331</xtag-item2></LI>
<LI><xtag-item2>REG_SR=761</xtag-item2></LI> <LI><xtag-item2>REG_SR=700</xtag-item2></LI>
<LI><xtag-item2>SELMUX2_1=28</xtag-item2></LI> <LI><xtag-item2>SELMUX2_1=24</xtag-item2></LI>
<LI><xtag-item2>SLICEL=88</xtag-item2></LI> <LI><xtag-item2>SLICEL=59</xtag-item2></LI>
<LI><xtag-item2>SLICEM=4</xtag-item2></LI> <LI><xtag-item2>SLICEM=4</xtag-item2></LI>
<LI><xtag-item2>SLICEX=291</xtag-item2></LI> <LI><xtag-item2>SLICEX=290</xtag-item2></LI>
</UL> </UL>
</xtag-group> </xtag-group>
</TD> </TD>
...@@ -265,9 +264,9 @@ ...@@ -265,9 +264,9 @@
<TD> <TD>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name> <xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL> <UL>
<LI><xtag-item3>CK=[CK:73] [CK_INV:0]</xtag-item3></LI> <LI><xtag-item3>CK=[CK:84] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:62] [SRINIT1:11]</xtag-item3></LI> <LI><xtag-item3>SRINIT=[SRINIT0:72] [SRINIT1:12]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:45] [SYNC:28]</xtag-item3></LI> <LI><xtag-item3>SYNC_ATTR=[ASYNC:49] [SYNC:35]</xtag-item3></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="IOBM_OUTBUF">IOBM_OUTBUF</xtag-group-name> <xtag-group><xtag-group-name name="IOBM_OUTBUF">IOBM_OUTBUF</xtag-group-name>
...@@ -291,9 +290,9 @@ ...@@ -291,9 +290,9 @@
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name> <xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name>
<UL> <UL>
<LI><xtag-item3>CLK=[CLK:4] [CLK_INV:0]</xtag-item3></LI> <LI><xtag-item3>CLK=[CLK:6] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LUT_OR_MEM=[RAM:4]</xtag-item3></LI> <LI><xtag-item3>LUT_OR_MEM=[RAM:6]</xtag-item3></LI>
<LI><xtag-item3>RAMMODE=[DPRAM32:4]</xtag-item3></LI> <LI><xtag-item3>RAMMODE=[SRL16:2] [DPRAM32:4]</xtag-item3></LI>
</UL> </UL>
</TD> </TD>
<TD> <TD>
...@@ -307,17 +306,17 @@ ...@@ -307,17 +306,17 @@
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name> <xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL> <UL>
<LI><xtag-item3>CK=[CK:761] [CK_INV:0]</xtag-item3></LI> <LI><xtag-item3>CK=[CK:700] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:761]</xtag-item3></LI> <LI><xtag-item3>LATCH_OR_FF=[FF:700]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:709] [SRINIT1:52]</xtag-item3></LI> <LI><xtag-item3>SRINIT=[SRINIT0:674] [SRINIT1:26]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:253] [SYNC:508]</xtag-item3></LI> <LI><xtag-item3>SYNC_ATTR=[ASYNC:221] [SYNC:479]</xtag-item3></LI>
</UL> </UL>
</TD> </TD>
<TD> <TD>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name> <xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL> <UL>
<LI><xtag-item3>CLK=[CLK:47] [CLK_INV:0]</xtag-item3></LI> <LI><xtag-item3>CLK=[CLK:33] [CLK_INV:0]</xtag-item3></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name> <xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
...@@ -327,7 +326,7 @@ ...@@ -327,7 +326,7 @@
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name> <xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL> <UL>
<LI><xtag-item3>CLK=[CLK:190] [CLK_INV:0]</xtag-item3></LI> <LI><xtag-item3>CLK=[CLK:198] [CLK_INV:0]</xtag-item3></LI>
</UL> </UL>
</xtag-group> </xtag-group>
</TD> </TD>
...@@ -339,49 +338,54 @@ ...@@ -339,49 +338,54 @@
<TD> <TD>
<xtag-group><xtag-group-name name="BUFG">BUFG</xtag-group-name> <xtag-group><xtag-group-name name="BUFG">BUFG</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>I0=4</xtag-item1></LI> <LI><xtag-item1>I0=2</xtag-item1></LI>
<LI><xtag-item1>O=4</xtag-item1></LI> <LI><xtag-item1>O=2</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="BUFG_BUFG">BUFG_BUFG</xtag-group-name> <xtag-group><xtag-group-name name="BUFG_BUFG">BUFG_BUFG</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>I0=4</xtag-item1></LI> <LI><xtag-item1>I0=2</xtag-item1></LI>
<LI><xtag-item1>O=4</xtag-item1></LI> <LI><xtag-item1>O=2</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name> <xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>CIN=47</xtag-item1></LI> <LI><xtag-item1>CIN=27</xtag-item1></LI>
<LI><xtag-item1>CO1=2</xtag-item1></LI> <LI><xtag-item1>CO1=2</xtag-item1></LI>
<LI><xtag-item1>CO2=1</xtag-item1></LI> <LI><xtag-item1>CO2=1</xtag-item1></LI>
<LI><xtag-item1>CO3=48</xtag-item1></LI> <LI><xtag-item1>CO3=27</xtag-item1></LI>
<LI><xtag-item1>CYINIT=13</xtag-item1></LI> <LI><xtag-item1>CYINIT=8</xtag-item1></LI>
<LI><xtag-item1>DI0=59</xtag-item1></LI> <LI><xtag-item1>DI0=35</xtag-item1></LI>
<LI><xtag-item1>DI1=58</xtag-item1></LI> <LI><xtag-item1>DI1=34</xtag-item1></LI>
<LI><xtag-item1>DI2=55</xtag-item1></LI> <LI><xtag-item1>DI2=32</xtag-item1></LI>
<LI><xtag-item1>DI3=48</xtag-item1></LI> <LI><xtag-item1>DI3=27</xtag-item1></LI>
<LI><xtag-item1>O0=56</xtag-item1></LI> <LI><xtag-item1>O0=31</xtag-item1></LI>
<LI><xtag-item1>O1=55</xtag-item1></LI> <LI><xtag-item1>O1=31</xtag-item1></LI>
<LI><xtag-item1>O2=54</xtag-item1></LI> <LI><xtag-item1>O2=30</xtag-item1></LI>
<LI><xtag-item1>O3=51</xtag-item1></LI> <LI><xtag-item1>O3=29</xtag-item1></LI>
<LI><xtag-item1>S0=60</xtag-item1></LI> <LI><xtag-item1>S0=35</xtag-item1></LI>
<LI><xtag-item1>S1=59</xtag-item1></LI> <LI><xtag-item1>S1=35</xtag-item1></LI>
<LI><xtag-item1>S2=58</xtag-item1></LI> <LI><xtag-item1>S2=33</xtag-item1></LI>
<LI><xtag-item1>S3=54</xtag-item1></LI> <LI><xtag-item1>S3=31</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name> <xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>CE=36</xtag-item1></LI> <LI><xtag-item1>CE=41</xtag-item1></LI>
<LI><xtag-item1>CK=73</xtag-item1></LI> <LI><xtag-item1>CK=84</xtag-item1></LI>
<LI><xtag-item1>D=73</xtag-item1></LI> <LI><xtag-item1>D=84</xtag-item1></LI>
<LI><xtag-item1>Q=73</xtag-item1></LI> <LI><xtag-item1>Q=84</xtag-item1></LI>
<LI><xtag-item1>SR=28</xtag-item1></LI> <LI><xtag-item1>SR=35</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name> <xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>0=12</xtag-item1></LI> <LI><xtag-item1>0=5</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="HARD1">HARD1</xtag-group-name>
<UL>
<LI><xtag-item1>1=2</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name> <xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
...@@ -391,7 +395,7 @@ ...@@ -391,7 +395,7 @@
<LI><xtag-item1>O=198</xtag-item1></LI> <LI><xtag-item1>O=198</xtag-item1></LI>
<LI><xtag-item1>PAD=327</xtag-item1></LI> <LI><xtag-item1>PAD=327</xtag-item1></LI>
<LI><xtag-item1>PADOUT=1</xtag-item1></LI> <LI><xtag-item1>PADOUT=1</xtag-item1></LI>
<LI><xtag-item1>T=44</xtag-item1></LI> <LI><xtag-item1>T=42</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="IOBM">IOBM</xtag-group-name> <xtag-group><xtag-group-name name="IOBM">IOBM</xtag-group-name>
...@@ -431,48 +435,48 @@ ...@@ -431,48 +435,48 @@
<UL> <UL>
<LI><xtag-item1>IN=198</xtag-item1></LI> <LI><xtag-item1>IN=198</xtag-item1></LI>
<LI><xtag-item1>OUT=198</xtag-item1></LI> <LI><xtag-item1>OUT=198</xtag-item1></LI>
<LI><xtag-item1>TRI=44</xtag-item1></LI> <LI><xtag-item1>TRI=42</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name> <xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>A1=46</xtag-item1></LI> <LI><xtag-item1>A1=23</xtag-item1></LI>
<LI><xtag-item1>A2=48</xtag-item1></LI> <LI><xtag-item1>A2=27</xtag-item1></LI>
<LI><xtag-item1>A3=126</xtag-item1></LI> <LI><xtag-item1>A3=98</xtag-item1></LI>
<LI><xtag-item1>A4=131</xtag-item1></LI> <LI><xtag-item1>A4=101</xtag-item1></LI>
<LI><xtag-item1>A5=65</xtag-item1></LI> <LI><xtag-item1>A5=56</xtag-item1></LI>
<LI><xtag-item1>O5=369</xtag-item1></LI> <LI><xtag-item1>O5=243</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name> <xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>A1=302</xtag-item1></LI> <LI><xtag-item1>A1=286</xtag-item1></LI>
<LI><xtag-item1>A2=472</xtag-item1></LI> <LI><xtag-item1>A2=409</xtag-item1></LI>
<LI><xtag-item1>A3=572</xtag-item1></LI> <LI><xtag-item1>A3=525</xtag-item1></LI>
<LI><xtag-item1>A4=870</xtag-item1></LI> <LI><xtag-item1>A4=745</xtag-item1></LI>
<LI><xtag-item1>A5=755</xtag-item1></LI> <LI><xtag-item1>A5=770</xtag-item1></LI>
<LI><xtag-item1>A6=930</xtag-item1></LI> <LI><xtag-item1>A6=848</xtag-item1></LI>
<LI><xtag-item1>O6=944</xtag-item1></LI> <LI><xtag-item1>O6=856</xtag-item1></LI>
</UL> </UL>
</TD> </TD>
<TD> <TD>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name> <xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>A1=4</xtag-item1></LI> <LI><xtag-item1>A1=6</xtag-item1></LI>
<LI><xtag-item1>A2=4</xtag-item1></LI> <LI><xtag-item1>A2=6</xtag-item1></LI>
<LI><xtag-item1>A3=4</xtag-item1></LI> <LI><xtag-item1>A3=6</xtag-item1></LI>
<LI><xtag-item1>A4=4</xtag-item1></LI> <LI><xtag-item1>A4=6</xtag-item1></LI>
<LI><xtag-item1>A5=4</xtag-item1></LI> <LI><xtag-item1>A5=6</xtag-item1></LI>
<LI><xtag-item1>CLK=4</xtag-item1></LI> <LI><xtag-item1>CLK=6</xtag-item1></LI>
<LI><xtag-item1>DI1=4</xtag-item1></LI> <LI><xtag-item1>DI1=6</xtag-item1></LI>
<LI><xtag-item1>O5=4</xtag-item1></LI> <LI><xtag-item1>O5=6</xtag-item1></LI>
<LI><xtag-item1>WA1=4</xtag-item1></LI> <LI><xtag-item1>WA1=4</xtag-item1></LI>
<LI><xtag-item1>WA2=4</xtag-item1></LI> <LI><xtag-item1>WA2=4</xtag-item1></LI>
<LI><xtag-item1>WA3=4</xtag-item1></LI> <LI><xtag-item1>WA3=4</xtag-item1></LI>
<LI><xtag-item1>WA4=4</xtag-item1></LI> <LI><xtag-item1>WA4=4</xtag-item1></LI>
<LI><xtag-item1>WA5=4</xtag-item1></LI> <LI><xtag-item1>WA5=4</xtag-item1></LI>
<LI><xtag-item1>WE=4</xtag-item1></LI> <LI><xtag-item1>WE=6</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name> <xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name>
...@@ -509,66 +513,67 @@ ...@@ -509,66 +513,67 @@
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name> <xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>CE=434</xtag-item1></LI> <LI><xtag-item1>CE=374</xtag-item1></LI>
<LI><xtag-item1>CK=761</xtag-item1></LI> <LI><xtag-item1>CK=700</xtag-item1></LI>
<LI><xtag-item1>D=761</xtag-item1></LI> <LI><xtag-item1>D=700</xtag-item1></LI>
<LI><xtag-item1>Q=761</xtag-item1></LI> <LI><xtag-item1>Q=700</xtag-item1></LI>
<LI><xtag-item1>SR=509</xtag-item1></LI> <LI><xtag-item1>SR=480</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name> <xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>0=28</xtag-item1></LI> <LI><xtag-item1>0=24</xtag-item1></LI>
<LI><xtag-item1>1=28</xtag-item1></LI> <LI><xtag-item1>1=24</xtag-item1></LI>
<LI><xtag-item1>OUT=28</xtag-item1></LI> <LI><xtag-item1>OUT=24</xtag-item1></LI>
<LI><xtag-item1>S0=28</xtag-item1></LI> <LI><xtag-item1>S0=24</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name> <xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>A=13</xtag-item1></LI> <LI><xtag-item1>A=9</xtag-item1></LI>
<LI><xtag-item1>A1=11</xtag-item1></LI> <LI><xtag-item1>A1=8</xtag-item1></LI>
<LI><xtag-item1>A2=15</xtag-item1></LI> <LI><xtag-item1>A2=10</xtag-item1></LI>
<LI><xtag-item1>A3=19</xtag-item1></LI> <LI><xtag-item1>A3=20</xtag-item1></LI>
<LI><xtag-item1>A4=61</xtag-item1></LI> <LI><xtag-item1>A4=36</xtag-item1></LI>
<LI><xtag-item1>A5=33</xtag-item1></LI> <LI><xtag-item1>A5=29</xtag-item1></LI>
<LI><xtag-item1>A6=74</xtag-item1></LI> <LI><xtag-item1>A6=45</xtag-item1></LI>
<LI><xtag-item1>AMUX=19</xtag-item1></LI> <LI><xtag-item1>AMUX=9</xtag-item1></LI>
<LI><xtag-item1>AQ=47</xtag-item1></LI> <LI><xtag-item1>AQ=31</xtag-item1></LI>
<LI><xtag-item1>AX=9</xtag-item1></LI> <LI><xtag-item1>AX=8</xtag-item1></LI>
<LI><xtag-item1>B=11</xtag-item1></LI> <LI><xtag-item1>B=8</xtag-item1></LI>
<LI><xtag-item1>B1=10</xtag-item1></LI> <LI><xtag-item1>B1=9</xtag-item1></LI>
<LI><xtag-item1>B2=12</xtag-item1></LI> <LI><xtag-item1>B2=9</xtag-item1></LI>
<LI><xtag-item1>B3=14</xtag-item1></LI> <LI><xtag-item1>B3=16</xtag-item1></LI>
<LI><xtag-item1>B4=58</xtag-item1></LI> <LI><xtag-item1>B4=35</xtag-item1></LI>
<LI><xtag-item1>B5=30</xtag-item1></LI> <LI><xtag-item1>B5=27</xtag-item1></LI>
<LI><xtag-item1>B6=71</xtag-item1></LI> <LI><xtag-item1>B6=43</xtag-item1></LI>
<LI><xtag-item1>BMUX=18</xtag-item1></LI> <LI><xtag-item1>BMUX=10</xtag-item1></LI>
<LI><xtag-item1>BQ=46</xtag-item1></LI> <LI><xtag-item1>BQ=29</xtag-item1></LI>
<LI><xtag-item1>BX=7</xtag-item1></LI> <LI><xtag-item1>BX=7</xtag-item1></LI>
<LI><xtag-item1>C1=6</xtag-item1></LI> <LI><xtag-item1>C1=10</xtag-item1></LI>
<LI><xtag-item1>C2=8</xtag-item1></LI> <LI><xtag-item1>C2=15</xtag-item1></LI>
<LI><xtag-item1>C3=20</xtag-item1></LI> <LI><xtag-item1>C3=33</xtag-item1></LI>
<LI><xtag-item1>C4=71</xtag-item1></LI> <LI><xtag-item1>C4=49</xtag-item1></LI>
<LI><xtag-item1>C5=45</xtag-item1></LI> <LI><xtag-item1>C5=40</xtag-item1></LI>
<LI><xtag-item1>C6=82</xtag-item1></LI> <LI><xtag-item1>C6=55</xtag-item1></LI>
<LI><xtag-item1>CE=22</xtag-item1></LI> <LI><xtag-item1>CE=12</xtag-item1></LI>
<LI><xtag-item1>CIN=47</xtag-item1></LI> <LI><xtag-item1>CIN=27</xtag-item1></LI>
<LI><xtag-item1>CLK=47</xtag-item1></LI> <LI><xtag-item1>CLK=33</xtag-item1></LI>
<LI><xtag-item1>CMUX=42</xtag-item1></LI> <LI><xtag-item1>CMUX=30</xtag-item1></LI>
<LI><xtag-item1>COUT=47</xtag-item1></LI> <LI><xtag-item1>COUT=27</xtag-item1></LI>
<LI><xtag-item1>CQ=47</xtag-item1></LI> <LI><xtag-item1>CQ=30</xtag-item1></LI>
<LI><xtag-item1>CX=31</xtag-item1></LI> <LI><xtag-item1>CX=26</xtag-item1></LI>
<LI><xtag-item1>D1=7</xtag-item1></LI> <LI><xtag-item1>D=2</xtag-item1></LI>
<LI><xtag-item1>D2=31</xtag-item1></LI> <LI><xtag-item1>D1=15</xtag-item1></LI>
<LI><xtag-item1>D3=33</xtag-item1></LI> <LI><xtag-item1>D2=27</xtag-item1></LI>
<LI><xtag-item1>D4=70</xtag-item1></LI> <LI><xtag-item1>D3=34</xtag-item1></LI>
<LI><xtag-item1>D5=43</xtag-item1></LI> <LI><xtag-item1>D4=49</xtag-item1></LI>
<LI><xtag-item1>D6=78</xtag-item1></LI> <LI><xtag-item1>D5=39</xtag-item1></LI>
<LI><xtag-item1>DMUX=15</xtag-item1></LI> <LI><xtag-item1>D6=54</xtag-item1></LI>
<LI><xtag-item1>DQ=42</xtag-item1></LI> <LI><xtag-item1>DMUX=7</xtag-item1></LI>
<LI><xtag-item1>DQ=27</xtag-item1></LI>
<LI><xtag-item1>DX=7</xtag-item1></LI> <LI><xtag-item1>DX=7</xtag-item1></LI>
<LI><xtag-item1>SR=28</xtag-item1></LI> <LI><xtag-item1>SR=25</xtag-item1></LI>
</UL> </UL>
</TD> </TD>
<TD> <TD>
...@@ -583,9 +588,9 @@ ...@@ -583,9 +588,9 @@
<LI><xtag-item1>A5=3</xtag-item1></LI> <LI><xtag-item1>A5=3</xtag-item1></LI>
<LI><xtag-item1>A6=3</xtag-item1></LI> <LI><xtag-item1>A6=3</xtag-item1></LI>
<LI><xtag-item1>AI=2</xtag-item1></LI> <LI><xtag-item1>AI=2</xtag-item1></LI>
<LI><xtag-item1>AMUX=1</xtag-item1></LI> <LI><xtag-item1>AMUX=2</xtag-item1></LI>
<LI><xtag-item1>AQ=1</xtag-item1></LI> <LI><xtag-item1>AQ=1</xtag-item1></LI>
<LI><xtag-item1>AX=2</xtag-item1></LI> <LI><xtag-item1>AX=3</xtag-item1></LI>
<LI><xtag-item1>B=2</xtag-item1></LI> <LI><xtag-item1>B=2</xtag-item1></LI>
<LI><xtag-item1>B1=3</xtag-item1></LI> <LI><xtag-item1>B1=3</xtag-item1></LI>
<LI><xtag-item1>B2=3</xtag-item1></LI> <LI><xtag-item1>B2=3</xtag-item1></LI>
...@@ -594,9 +599,9 @@ ...@@ -594,9 +599,9 @@
<LI><xtag-item1>B5=3</xtag-item1></LI> <LI><xtag-item1>B5=3</xtag-item1></LI>
<LI><xtag-item1>B6=3</xtag-item1></LI> <LI><xtag-item1>B6=3</xtag-item1></LI>
<LI><xtag-item1>BI=2</xtag-item1></LI> <LI><xtag-item1>BI=2</xtag-item1></LI>
<LI><xtag-item1>BMUX=1</xtag-item1></LI> <LI><xtag-item1>BMUX=2</xtag-item1></LI>
<LI><xtag-item1>BQ=1</xtag-item1></LI> <LI><xtag-item1>BQ=1</xtag-item1></LI>
<LI><xtag-item1>BX=1</xtag-item1></LI> <LI><xtag-item1>BX=2</xtag-item1></LI>
<LI><xtag-item1>C=1</xtag-item1></LI> <LI><xtag-item1>C=1</xtag-item1></LI>
<LI><xtag-item1>C1=4</xtag-item1></LI> <LI><xtag-item1>C1=4</xtag-item1></LI>
<LI><xtag-item1>C2=4</xtag-item1></LI> <LI><xtag-item1>C2=4</xtag-item1></LI>
...@@ -624,49 +629,49 @@ ...@@ -624,49 +629,49 @@
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name> <xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>A=114</xtag-item1></LI> <LI><xtag-item1>A=115</xtag-item1></LI>
<LI><xtag-item1>A1=101</xtag-item1></LI> <LI><xtag-item1>A1=83</xtag-item1></LI>
<LI><xtag-item1>A2=143</xtag-item1></LI> <LI><xtag-item1>A2=109</xtag-item1></LI>
<LI><xtag-item1>A3=182</xtag-item1></LI> <LI><xtag-item1>A3=147</xtag-item1></LI>
<LI><xtag-item1>A4=200</xtag-item1></LI> <LI><xtag-item1>A4=167</xtag-item1></LI>
<LI><xtag-item1>A5=197</xtag-item1></LI> <LI><xtag-item1>A5=182</xtag-item1></LI>
<LI><xtag-item1>A6=205</xtag-item1></LI> <LI><xtag-item1>A6=189</xtag-item1></LI>
<LI><xtag-item1>AMUX=44</xtag-item1></LI> <LI><xtag-item1>AMUX=36</xtag-item1></LI>
<LI><xtag-item1>AQ=169</xtag-item1></LI> <LI><xtag-item1>AQ=146</xtag-item1></LI>
<LI><xtag-item1>AX=65</xtag-item1></LI> <LI><xtag-item1>AX=64</xtag-item1></LI>
<LI><xtag-item1>B=72</xtag-item1></LI> <LI><xtag-item1>B=58</xtag-item1></LI>
<LI><xtag-item1>B1=64</xtag-item1></LI> <LI><xtag-item1>B1=57</xtag-item1></LI>
<LI><xtag-item1>B2=99</xtag-item1></LI> <LI><xtag-item1>B2=81</xtag-item1></LI>
<LI><xtag-item1>B3=129</xtag-item1></LI> <LI><xtag-item1>B3=110</xtag-item1></LI>
<LI><xtag-item1>B4=140</xtag-item1></LI> <LI><xtag-item1>B4=129</xtag-item1></LI>
<LI><xtag-item1>B5=142</xtag-item1></LI> <LI><xtag-item1>B5=148</xtag-item1></LI>
<LI><xtag-item1>B6=142</xtag-item1></LI> <LI><xtag-item1>B6=147</xtag-item1></LI>
<LI><xtag-item1>BMUX=35</xtag-item1></LI> <LI><xtag-item1>BMUX=27</xtag-item1></LI>
<LI><xtag-item1>BQ=135</xtag-item1></LI> <LI><xtag-item1>BQ=151</xtag-item1></LI>
<LI><xtag-item1>BX=61</xtag-item1></LI> <LI><xtag-item1>BX=58</xtag-item1></LI>
<LI><xtag-item1>C=52</xtag-item1></LI> <LI><xtag-item1>C=81</xtag-item1></LI>
<LI><xtag-item1>C1=78</xtag-item1></LI> <LI><xtag-item1>C1=68</xtag-item1></LI>
<LI><xtag-item1>C2=98</xtag-item1></LI> <LI><xtag-item1>C2=86</xtag-item1></LI>
<LI><xtag-item1>C3=123</xtag-item1></LI> <LI><xtag-item1>C3=114</xtag-item1></LI>
<LI><xtag-item1>C4=132</xtag-item1></LI> <LI><xtag-item1>C4=133</xtag-item1></LI>
<LI><xtag-item1>C5=134</xtag-item1></LI> <LI><xtag-item1>C5=149</xtag-item1></LI>
<LI><xtag-item1>C6=133</xtag-item1></LI> <LI><xtag-item1>C6=148</xtag-item1></LI>
<LI><xtag-item1>CE=101</xtag-item1></LI> <LI><xtag-item1>CE=96</xtag-item1></LI>
<LI><xtag-item1>CLK=190</xtag-item1></LI> <LI><xtag-item1>CLK=198</xtag-item1></LI>
<LI><xtag-item1>CMUX=33</xtag-item1></LI> <LI><xtag-item1>CMUX=26</xtag-item1></LI>
<LI><xtag-item1>CQ=146</xtag-item1></LI> <LI><xtag-item1>CQ=129</xtag-item1></LI>
<LI><xtag-item1>CX=58</xtag-item1></LI> <LI><xtag-item1>CX=58</xtag-item1></LI>
<LI><xtag-item1>D=86</xtag-item1></LI> <LI><xtag-item1>D=85</xtag-item1></LI>
<LI><xtag-item1>D1=68</xtag-item1></LI> <LI><xtag-item1>D1=58</xtag-item1></LI>
<LI><xtag-item1>D2=98</xtag-item1></LI> <LI><xtag-item1>D2=92</xtag-item1></LI>
<LI><xtag-item1>D3=128</xtag-item1></LI> <LI><xtag-item1>D3=125</xtag-item1></LI>
<LI><xtag-item1>D4=138</xtag-item1></LI> <LI><xtag-item1>D4=147</xtag-item1></LI>
<LI><xtag-item1>D5=140</xtag-item1></LI> <LI><xtag-item1>D5=164</xtag-item1></LI>
<LI><xtag-item1>D6=145</xtag-item1></LI> <LI><xtag-item1>D6=167</xtag-item1></LI>
<LI><xtag-item1>DMUX=39</xtag-item1></LI> <LI><xtag-item1>DMUX=26</xtag-item1></LI>
<LI><xtag-item1>DQ=123</xtag-item1></LI> <LI><xtag-item1>DQ=151</xtag-item1></LI>
<LI><xtag-item1>DX=60</xtag-item1></LI> <LI><xtag-item1>DX=62</xtag-item1></LI>
<LI><xtag-item1>SR=134</xtag-item1></LI> <LI><xtag-item1>SR=135</xtag-item1></LI>
</UL> </UL>
</TD> </TD>
<TD> <TD>
...@@ -789,13 +794,90 @@ ...@@ -789,13 +794,90 @@
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI> <LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI> <LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI> <LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR> </xtag-section></UL></TD></TR>
</TABLE> </TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR> &nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
<tr> <tr>
<td><xtag-program-name>_impact</xtag-program-name></td> <td><xtag-program-name>_impact</xtag-program-name></td>
<td><xtag-total-run-started>12</xtag-total-run-started></td> <td><xtag-total-run-started>23</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td> <td><xtag-total-run-finished>19</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td> <td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
...@@ -804,8 +886,8 @@ ...@@ -804,8 +886,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>bitgen</xtag-program-name></td> <td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>11</xtag-total-run-started></td> <td><xtag-total-run-started>23</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td> <td><xtag-total-run-finished>23</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td> <td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
...@@ -814,8 +896,8 @@ ...@@ -814,8 +896,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>map</xtag-program-name></td> <td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>11</xtag-total-run-started></td> <td><xtag-total-run-started>23</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td> <td><xtag-total-run-finished>23</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td> <td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
...@@ -824,8 +906,8 @@ ...@@ -824,8 +906,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>ngc2edif</xtag-program-name></td> <td><xtag-program-name>ngc2edif</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td> <td><xtag-total-run-started>4</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td> <td><xtag-total-run-finished>4</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td> <td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
...@@ -834,8 +916,8 @@ ...@@ -834,8 +916,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td> <td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>11</xtag-total-run-started></td> <td><xtag-total-run-started>24</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td> <td><xtag-total-run-finished>24</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td> <td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
...@@ -844,8 +926,8 @@ ...@@ -844,8 +926,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>par</xtag-program-name></td> <td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>11</xtag-total-run-started></td> <td><xtag-total-run-started>23</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td> <td><xtag-total-run-finished>23</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td> <td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
...@@ -854,8 +936,8 @@ ...@@ -854,8 +936,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>trce</xtag-program-name></td> <td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>11</xtag-total-run-started></td> <td><xtag-total-run-started>23</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td> <td><xtag-total-run-finished>23</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td> <td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
...@@ -864,8 +946,8 @@ ...@@ -864,8 +946,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>xst</xtag-program-name></td> <td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>10</xtag-total-run-started></td> <td><xtag-total-run-started>26</xtag-total-run-started></td>
<td><xtag-total-run-finished>10</xtag-total-run-finished></td> <td><xtag-total-run-finished>26</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td> <td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
...@@ -897,7 +979,7 @@ ...@@ -897,7 +979,7 @@
<TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2010-12-15T15:02:16</xtag-design-property-value></TD> <TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2010-12-15T15:02:16</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>F6031676C5FE434A8E9F8A1057A8E48F</xtag-design-property-value></TD> </TR><TR><TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>F6031676C5FE434A8E9F8A1057A8E48F</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>12</xtag-process-property-value></TD> <TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>24</xtag-process-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD> </TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD> <TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
...@@ -927,96 +1009,96 @@ ...@@ -927,96 +1009,96 @@
<xtag-section name="UnisimStatistics"> <xtag-section name="UnisimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR> <TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>195</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>165</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>102</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>104</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDPE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDPE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>135</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>170</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>342</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>310</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>26</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>26</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDSE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>33</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDSE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>8</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>76</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>77</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUFGDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>6</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUFGDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>6</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>32</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>23</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>32</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>32</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUFDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUFDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>197</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>86</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>168</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>211</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>130</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>149</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>116</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>85</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>148</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>123</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>298</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>284</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>220</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>128</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>24</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>152</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>154</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUFDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUFDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-preunisim-param-name>=<xtag-preunisim-param-value>32</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-preunisim-param-name>=<xtag-preunisim-param-value>30</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAM16X1D</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAM16X1D</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAM32M</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAM32M</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-preunisim-param-name>=<xtag-preunisim-param-value>6</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-preunisim-param-name>=<xtag-preunisim-param-value>8</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>216</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>121</xtag-preunisim-param-value></TD>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR> <TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>195</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>165</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>102</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>104</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDPE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDPE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>135</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>170</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>342</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>310</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>26</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>26</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDSE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>33</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDSE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>8</xtag-postunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>157</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>158</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFGDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>6</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFGDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>6</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>32</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>23</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>197</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>86</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>168</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>211</xtag-postunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>130</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>149</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>116</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>85</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>148</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>123</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>298</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>284</xtag-postunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>220</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>128</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>24</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>152</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>154</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>64</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>62</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFTDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFTDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_RAM32M</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_RAM32M</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-postunisim-param-name>=<xtag-postunisim-param-value>6</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-postunisim-param-name>=<xtag-postunisim-param-value>8</xtag-postunisim-param-value></TD>
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<TD><xtag-postunisim-param-name>NGDBUILD_NUM_TS_TIMESPEC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_TS_TIMESPEC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
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</xtag-section></TABLE> </xtag-section></TABLE>
&nbsp;<BR></BODY></HTML> &nbsp;<BR></BODY></HTML>
trunk/firmware/XilinxISE/SystemFpga/webtalk.log
View file @ cb70c6e4
...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information Project Information
-------------------- --------------------
ProjectID=F6031676C5FE434A8E9F8A1057A8E48F ProjectID=F6031676C5FE434A8E9F8A1057A8E48F
ProjectIteration=12 ProjectIteration=24
WebTalk Summary WebTalk Summary
---------------- ----------------
...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled. ...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON. INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON. INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-20T17:37:16. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2011-01-06T13:58:42. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
trunk/firmware/XilinxISE/SystemFpga/webtalk_pn.xml
View file @ cb70c6e4
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Mon Dec 20 17:36:42 2010"> <application name="pn" timeStamp="Thu Jan 06 13:57:59 2011">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/> <property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/>
<property name="ProjectIteration" value="12" type="project"/> <property name="ProjectIteration" value="24" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/> <property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/> <property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/>
</section> </section>
...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq ...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/> <property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/>
<property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/> <property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/>
<property name="PROP_intWbtProjectIteration" value="12" type="process"/> <property name="PROP_intWbtProjectIteration" value="24" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> <property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
......
trunk/hdl/design/SystemFpga.v
View file @ cb70c6e4
...@@ -399,12 +399,19 @@ Monostable i_Debug4Monostable( ...@@ -399,12 +399,19 @@ Monostable i_Debug4Monostable(
assign FpLed_onb8[0] = VmeAccessForLed ? 1'b0 : 1'bz; assign FpLed_onb8[0] = VmeAccessForLed ? 1'b0 : 1'bz;
assign FpLed_onb8[1] = (|VmeIrq_ob7) ? 1'b0 : 1'bz; assign FpLed_onb8[1] = (|VmeIrq_ob7) ? 1'b0 : 1'bz;
assign FpLed_onb8[2] = (^{VmeGa_ib5n, ~VmeGaP_in} | ~UseGa_i) ? 1'b0 : 1'bz; assign FpLed_onb8[2] = (^{VmeGa_ib5n, ~VmeGaP_in} | ~UseGa_i) ? 1'b0 : 1'bz;
assign FpLed_onb8[3] = (Si57xDivided||RstForLed) ? 1'b0 : 1'bz; assign FpLed_onb8[3] = (Si57xDivided||Rst_rq) ? 1'b0 : 1'bz;
assign FpLed_onb8[4] = DebugForLed1 ? 1'b0 : 1'bz; //assign FpLed_onb8[4] = DebugForLed1 ? 1'b0 : 1'bz;
assign FpLed_onb8[5] = DebugForLed2 ? 1'b0 : 1'bz; //assign FpLed_onb8[5] = DebugForLed2 ? 1'b0 : 1'bz;
assign FpLed_onb8[6] = DebugForLed3 ? 1'b0 : 1'bz; //assign FpLed_onb8[6] = DebugForLed3 ? 1'b0 : 1'bz;
assign FpLed_onb8[7] = DebugForLed4 ? 1'b0 : 1'bz; //assign FpLed_onb8[7] = DebugForLed4 ? 1'b0 : 1'bz;
wire [3:0] VmeDebug_b4;
assign FpLed_onb8[4] = VmeDebug_b4[0] ? 1'b0 : 1'bz;
assign FpLed_onb8[5] = VmeDebug_b4[1] ? 1'b0 : 1'bz;
assign FpLed_onb8[6] = VmeDebug_b4[2] ? 1'b0 : 1'bz;
assign FpLed_onb8[7] = VmeDebug_b4[3] ? 1'b0 : 1'bz;
always @(posedge Clk_k) begin always @(posedge Clk_k) begin
Debug1 <= Cyc && StbGenericOutputRegs && We; Debug1 <= Cyc && StbGenericOutputRegs && We;
...@@ -533,7 +540,8 @@ VmeToWishBone i_VmeInterface( ...@@ -533,7 +540,8 @@ VmeToWishBone i_VmeInterface(
.UseGa_i(UseGa_i), .UseGa_i(UseGa_i),
.ManualAddress_ib5(ManualAddress_ib5), .ManualAddress_ib5(ManualAddress_ib5),
.AssertInterrupt_i(AssertInterrupt), .AssertInterrupt_i(AssertInterrupt),
.ClearInt_op(IntAcknowledged)); .ClearInt_op(IntAcknowledged),
.DebugOut_ob4(VmeDebug_b4));
InterruptManagerWB i_InterruptManager( InterruptManagerWB i_InterruptManager(
.Clk_ik(Clk_k), .Clk_ik(Clk_k),
......
trunk/hdl/design/VmeToWishBone.v
View file @ cb70c6e4
...@@ -33,8 +33,10 @@ module VmeToWishBone( ...@@ -33,8 +33,10 @@ module VmeToWishBone(
input UseGa_i, input UseGa_i,
input [4:0] ManualAddress_ib5, input [4:0] ManualAddress_ib5,
input AssertInterrupt_i, input AssertInterrupt_i,
output reg ClearInt_op); output reg ClearInt_op,
output [3:0] DebugOut_ob4);
// Board Base Address // Board Base Address
wire GapError = ^{~VmeGap_i, VmeGa_ib5}; wire GapError = ^{~VmeGap_i, VmeGa_ib5};
...@@ -74,6 +76,7 @@ end ...@@ -74,6 +76,7 @@ end
// State Machine // State Machine
reg [29:0] TimoutCounter_cb30;
reg [1:0] State_q, NextState_a; reg [1:0] State_q, NextState_a;
localparam s_Idle = 2'b00, localparam s_Idle = 2'b00,
...@@ -90,11 +93,11 @@ always @* begin ...@@ -90,11 +93,11 @@ always @* begin
if (VmeRWAccess_a) NextState_a = VmeWr_in ? s_Read : s_Write; if (VmeRWAccess_a) NextState_a = VmeWr_in ? s_Read : s_Write;
else if (VmeIntAckAccess_a) NextState_a = s_IntAck; else if (VmeIntAckAccess_a) NextState_a = s_IntAck;
s_Write: s_Write:
if (~Ack_i && ~Stb_oq && ~VmeRWAccess_a) NextState_a = s_Idle; if ((~Ack_i && ~Stb_oq && ~VmeRWAccess_a) || & TimoutCounter_cb30) NextState_a = s_Idle;
s_Read: s_Read:
if (~Ack_i && ~Stb_oq && ~VmeRWAccess_a) NextState_a = s_Idle; if ((~Ack_i && ~Stb_oq && ~VmeRWAccess_a) || & TimoutCounter_cb30) NextState_a = s_Idle;
s_IntAck: s_IntAck:
if (a_Ds1_q && a_IAckIn_q) NextState_a = s_Idle; if ((a_Ds1_q && a_IAckIn_q) || & TimoutCounter_cb30) NextState_a = s_Idle;
default: default:
NextState_a = s_Idle; NextState_a = s_Idle;
endcase endcase
...@@ -113,14 +116,16 @@ always @(posedge Clk_ik) begin ...@@ -113,14 +116,16 @@ always @(posedge Clk_ik) begin
Stb_oq <= 1'b0; Stb_oq <= 1'b0;
Cyc_oq <= 1'b0; Cyc_oq <= 1'b0;
VmeDtAck_oqn <= 1'b1; VmeDtAck_oqn <= 1'b1;
VmeDataReg_qb32 <= 32'h0; VmeDataReg_qb32 <= 32'h0;
VmeDataRegOe <= 1'b0; VmeDataRegOe <= 1'b0;
VmeDataOe_oq <= 1'b0; VmeDataOe_oq <= 1'b0;
VmeDataDir_oq <= 1'b0; VmeDataDir_oq <= 1'b0;
ClearInt_op <= 1'b0; ClearInt_op <= 1'b0;
VmeIAckOutn_oqn <= 1'b1; VmeIAckOutn_oqn <= 1'b1;
TimoutCounter_cb30 <= 30'h0;
end else case (State_q) end else case (State_q)
s_Idle: begin s_Idle: begin
TimoutCounter_cb30 <= 30'h0;
Adr_obq22 <= 22'h0; Adr_obq22 <= 22'h0;
Dat_obq32 <= 32'h0; Dat_obq32 <= 32'h0;
We_oq <= 1'b0; We_oq <= 1'b0;
...@@ -156,6 +161,7 @@ always @(posedge Clk_ik) begin ...@@ -156,6 +161,7 @@ always @(posedge Clk_ik) begin
end end
end end
s_Write: begin s_Write: begin
TimoutCounter_cb30 <= TimoutCounter_cb30 + 1'b1;
if (Ack_i) begin if (Ack_i) begin
Stb_oq <= 1'b0; Stb_oq <= 1'b0;
Cyc_oq <= 1'b0; Cyc_oq <= 1'b0;
...@@ -164,6 +170,7 @@ always @(posedge Clk_ik) begin ...@@ -164,6 +170,7 @@ always @(posedge Clk_ik) begin
end end
end end
s_Read: begin s_Read: begin
TimoutCounter_cb30 <= TimoutCounter_cb30 + 1'b1;
if (Ack_i && Stb_oq) begin if (Ack_i && Stb_oq) begin
Stb_oq <= 1'b0; Stb_oq <= 1'b0;
Cyc_oq <= 1'b0; Cyc_oq <= 1'b0;
...@@ -174,6 +181,7 @@ always @(posedge Clk_ik) begin ...@@ -174,6 +181,7 @@ always @(posedge Clk_ik) begin
if (NextState_a==s_Idle) VmeDataRegOe <= 1'b0; if (NextState_a==s_Idle) VmeDataRegOe <= 1'b0;
end end
s_IntAck: begin s_IntAck: begin
TimoutCounter_cb30 <= TimoutCounter_cb30 + 1'b1;
ClearInt_op <= 1'b0; ClearInt_op <= 1'b0;
VmeDataRegOe <= 1'b1; VmeDataRegOe <= 1'b1;
VmeDtAck_oqn <= ~VmeDataRegOe; VmeDtAck_oqn <= ~VmeDataRegOe;
...@@ -183,6 +191,7 @@ always @(posedge Clk_ik) begin ...@@ -183,6 +191,7 @@ always @(posedge Clk_ik) begin
end end
end end
default: begin default: begin
TimoutCounter_cb30 <= 30'h0;
Adr_obq22 <= 22'h0; Adr_obq22 <= 22'h0;
Dat_obq32 <= 32'h0; Dat_obq32 <= 32'h0;
We_oq <= 1'b0; We_oq <= 1'b0;
...@@ -199,4 +208,6 @@ always @(posedge Clk_ik) begin ...@@ -199,4 +208,6 @@ always @(posedge Clk_ik) begin
endcase endcase
end end
assign DebugOut_ob4 = {VmeDs2_ia, VmeDs1_ia, 1'b1, 1'b1};
endmodule endmodule
trunk/hdl/design/XilinxWrappers/SFpga.v
View file @ cb70c6e4
...@@ -250,7 +250,7 @@ SystemFpga i_Core( ...@@ -250,7 +250,7 @@ SystemFpga i_Core(
.VmeIack_in(VmeIack_in), .VmeIack_in(VmeIack_in),
.VmeIackIn_in(VmeIackIn_in), .VmeIackIn_in(VmeIackIn_in),
.VmeIackOut_on(VmeIackOut_on), .VmeIackOut_on(VmeIackOut_on),
.VmeDs_inb2(VmeDs_i), .VmeDs_inb2(VmeDs_inb2),
.VmeAOeN_oen(VmeAOeN_oen), .VmeAOeN_oen(VmeAOeN_oen),
.VmeADirVfcToVme_o(VmeADirVfcToVme_o), .VmeADirVfcToVme_o(VmeADirVfcToVme_o),
.VmeRetryOe_oe(VmeRetryOe_oe), .VmeRetryOe_oe(VmeRetryOe_oe),
......
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