Minutes from the BI Technical Board of the 18th of June 2009
- The Application FPGA should be connected also to the P2 connector's
user pins.
- Some of the P2 user pins will also be connected to unused FMC
connector pins to be able to reroute analog signals from P0 to P2.
- The analog footprint of our existing mezzanine should be
investigated to see if it is possible for BI to use the standard FMC
form factor. <= action BI mezzanine developers and Andrea
- A 3 FPGA solution has been suggested by Christos as an alternative
to a 2 FPGA system. The pros and cons of such solution should be
investigated <= Action Christos, Andrea, Javier, Pablo
- It was requested by Ralph to have a TCP-HTTP server on board. The
case of use and the implication of this should be investigated <=
action Ralph for
justification, Andrea + TB + CO for decision
- It was proposed by David to have a DSP on board <= action David for
justification, Andrea + TB + CO for decision
- In the current proposal the JTAG and I2C busses to the mezzanine
were controlled by the system FPGA. It was requested to have the
possibility to deisy chain it with the other board components and
namely the system and te application FPGA. <= action David for
justification, Andrea + TB + CO for decision
- On the prototype of the board the power supplies originally coming
from the P0 connectors will be generated on board to evaluate their
quality in this configuration. The possibility to bypass the
generation modules and get the PS from the P0 will be assured by 0Ω
resistors networks
- The possibility to have a stricter symmetry between the VME and PCIe
carriers should be investigated to see if it could lead to a 1 to 1
sharing of the firmware. <= action Andrea, Pablo, Javier
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