Description
White Rabbit (WR) is a solution to the generic problem of transferring
data in a fast, deterministic and safe manner. Although its initial
scope is mainly targeted at timing systems for experimental physics
facilities, care has been taken to come up with a solution which is as
generic as possible. The aim is to be able to synchronize ~1000 nodes
with sub-ns accuracy over fiber and copper lengths of up to 10 km. The
key technologies used are physical layer syntonization (clock recovery)
and PTP (IEEE 1588).
This OHR project is both the home of the hardware design for the White
Rabbit switch and an umbrella for general WR-related
documents and discussion. In particular, the
Documents tab
contains key working documents such as the White Rabbit specification as
well as publications, presentations and other useful material. Several
potential users have expressed interest in WR, and some
commercial companies are collaborating in design tasks
and will commercialize the results.
The WR switch software is dealt with in a separate subproject.
Work so far
Date | Event |
15-02-2008 | White Rabbit workshop 1. Project start. |
27-10-2008 | White Rabbit workshop 2. |
20-07-2009 | White Rabbit workshop 3. Demonstration of a stabilized link. |
01-04-2010 | Switch MCH card v2 PCB ready. |
24-06-2010 | Mini-backplane PCB ready. |
20-09-2010 | Kick-off of 1st two-month development cycle. |
22-09-2010 | Enclosure for mini-backplane and MCH v2 ready. |
10-12-2010 | First developer meeting. Basic Ethernet switching demonstrated. |
14-04-2011 | 4th WR Workshop. PTP working on a WR node. |
Ongoing work and road map
The main goal in the medium term is to have a working WR switch by the end of 2011. The next workshop will be sometime in September. By then we should have a new version of the hardware for the switch (v3). During these months, development will be focused on the following areas:
- WR switch
- V3 hardware, including 18-port mini-backplane (Seven Solutions, Tomasz).
- Switch management software (Integrasys, Alessandro).
- Porting VHDL to v3 hardware (Virtex 6) (Tomasz, Seven Solutions).
- Switch diagnostics software (César).
- HW support for RSTP and High Priority traffic bypass (Maciej).
- Switch software kit (Alessandro).
- Switch testing software (Alessandro, César).
- Switchover in clock recovery PLL for increased reliability of clock transmission (Tomasz).
- Switching core upgrade to use QDR memory (Tomasz).
- WR nodes
- Node specification (Tibor, Sergio, Jean-Claude, César, Rodney).
- Forward Error Correction (FEC) HDL (Maciej).
- LM32 debugger and Xilinx support (Wesley).
- FEC software (Wesley).
- Etherbone HDL (Mathias).
- Etherbone documentation (Wesley, Mathias).
- WR PTP core. See if this core can be a PTP master as well (Greg D.).
- Other
- WR specification update (Maciej, Javier, Peter, Henk).
- Work on copper support for the switch mini-backplane and the node (Tomasz, Greg D.).
- Beam-synchronous timing using WR, i.e. transmitting RF signals with WR (Pablo, Pedro, Mathias).
- Non-symmetric delay calibration (Peter, Henk, Javier).
- PLL optimization (Pedro).
- PTP daemon (Alessandro, Marco).
- Specification of White Rabbit Fabric (WRF) using Wishbone (Tomasz).
The associated software developments for the WR switch can be seen in the software project wiki.