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Commit d7c7b52e authored by Tristan Gingold's avatar Tristan Gingold
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Merge branch 'peter_lpdc_via_wishbone_mdio' into 'wrpc-v5' 

Update family7 gtx-lp and gthe4-lp, now using lpdc via wishbone mdio

See merge request !9
parents bb25c738 0e3962b4
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    platform/xilinx/wr_gtp_phy/Manifest.py
    View file @ d7c7b52e
    ......@@ -51,15 +51,24 @@ xilinx_ip_common = [
    ];
    xilinx_ip_gthe4_lp = [
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.v",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gtwizard_top.v",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.xdc",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gtwizard_gthe4.v",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_ooc.xdc",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_v1_7_gthe4_channel.v"
    ];
    xilinx_ip_gthe4_lp_125 = [
    "xilinx-ip/gthe4_lp/phy_ref_clk_125/gtwizard_ultrascale_2.v",
    "xilinx-ip/gthe4_lp/phy_ref_clk_125/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
    "xilinx-ip/gthe4_lp/phy_ref_clk_125/gtwizard_ultrascale_2_ooc.xdc",
    ];
    xilinx_ip_gthe4_lp_100 = [
    "xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2.v",
    "xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
    "xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_ooc.xdc",
    ];
    xilinx_ip_gthe4_common_lp = [
    "xilinx-ip/gthe4_lp/common/gtwizard_ultrascale_v1_7_bit_sync.v",
    "xilinx-ip/gthe4_lp/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v",
    ......@@ -162,6 +171,15 @@ elif (syn_device[0:6].upper()=="XCAU10" or # Artix Ultrascale+ AU10P AU15P GTH
    files.extend([
    "family7-gthe4-lp/wr_gthe4_phy_family7_lp.vhd",
    "family7-gtx-lp/gtx_comma_detect_lp.vhd",
    "common/lpdc_mdio_regs.vhd",
    ]);
    files.extend( xilinx_ip_gthe4_lp ); # Note that gthe4 depend on Vivado version
    files.extend( xilinx_ip_gthe4_common_lp ); # and instantiate its specific common files
    files.extend( xilinx_ip_gthe4_lp ); # Note that gthe4 depend on Vivado version
    files.extend( xilinx_ip_gthe4_common_lp ); # and instantiate its specific common files
    # PHY reference clock defaults to 125 MHz; check if 100 MHz is defined
    try:
    if (phy_ref_clk=="100"):
    files.extend( xilinx_ip_gthe4_lp_100 );
    else:
    files.extend( xilinx_ip_gthe4_lp_125 ); # if phy_clk_ref exists but is other than "100"
    except:
    files.extend( xilinx_ip_gthe4_lp_125 ); # if phy_clk_ref does not exists
    platform/xilinx/wr_gtp_phy/family7-gthe4-lp/wr_gthe4_phy_family7_lp.vhd
    View file @ d7c7b52e
    ......@@ -6,7 +6,7 @@
    -- Author : Peter Jansweijer, Tomasz Wlostowski
    -- Company : CERN BE-CO-HT
    -- Created : 2013-04-08
    -- Last update: 2023-01-27
    -- Last update: 2023-06-06
    -- Platform : FPGA-generic
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    ......@@ -37,6 +37,7 @@
    -- Revisions :
    -- Date Version Author Description
    -- 2013-04-08 0.1 PeterJ Initial release based on "wr_gtx_phy_virtex6.vhd" and "wr_gtx_phy_family7_lp.vhd"
    -- 2013-06-06 0.2 PeterJ use WB bus for LPDC regs
    -------------------------------------------------------------------------------
    library ieee;
    ......@@ -48,6 +49,8 @@ use unisim.vcomponents.all;
    use work.gencores_pkg.all;
    use work.disparity_gen_pkg.all;
    use work.wishbone_pkg.all;
    use work.lpdc_mdio_regs_pkg.all;
    entity wr_gthe4_phy_family7_lp is
    ......@@ -65,6 +68,10 @@ entity wr_gthe4_phy_family7_lp is
    -- Note: DMTD clock is also used as free running clock
    clk_dmtd_i : in std_logic;
    -- systemc clock for MDIO registers
    clk_sys_i : in std_logic;
    rst_sys_n_i : in std_logic;
    -- TX path, synchronous to tx_out_clk_o (62.5 MHz):
    tx_out_clk_o : out std_logic;
    tx_locked_o : out std_logic;
    ......@@ -113,16 +120,16 @@ entity wr_gthe4_phy_family7_lp is
    loopen_i : in std_logic;
    tx_prbs_sel_i : in std_logic_vector(2 downto 0);
    lpc_ctrl_i : in std_logic_vector(15 downto 0);
    lpc_stat_o : out std_logic_vector(15 downto 0);
    pad_txn_o : out std_logic;
    pad_txp_o : out std_logic;
    pad_rxn_i : in std_logic := '0';
    pad_rxp_i : in std_logic := '0';
    rdy_o : out std_logic
    rdy_o : out std_logic;
    mdio_slave_i : in t_wishbone_slave_in;
    mdio_slave_o : out t_wishbone_slave_out
    );
    end wr_gthe4_phy_family7_lp;
    ......@@ -229,7 +236,7 @@ architecture rtl of wr_gthe4_phy_family7_lp is
    signal tx_out_clk : std_logic;
    signal tx_out_clk_sampled : std_logic;
    signal rx_rec_clk : std_logic;
    signal rx_rec_clk_sampled : std_logic;
    signal rx_rec_clk_sampled : std_logic;
    signal serdes_ready_a : std_logic;
    signal serdes_ready_txclk : std_logic;
    ......@@ -253,42 +260,38 @@ architecture rtl of wr_gthe4_phy_family7_lp is
    signal cur_disp : t_8b10b_disparity;
    signal tx_data_8b10b : std_logic_vector(19 downto 0);
    signal tx_sw_reset : std_logic;
    signal tx_enable : std_logic;
    signal tx_enable_txclk : std_logic;
    signal rx_enable : std_logic;
    signal rx_sw_reset : std_logic;
    signal cpll_sw_reset : std_logic;
    signal cd_reset : std_logic;
    signal gth_tx_reset_a : std_logic;
    signal gth_rx_reset_a : std_logic;
    signal gth_loopback : std_logic_vector(2 downto 0) := "000";
    signal comma_target_pos : std_logic_vector(4 downto 0);
    signal comma_current_pos : std_logic_vector(4 downto 0);
    signal rx_data_raw : std_logic_vector(19 downto 0);
    signal rx_data_decode : std_logic_vector(19 downto 0);
    signal rx_code_err : std_logic_vector(1 downto 0);
    signal link_up : std_logic;
    signal link_aligned : std_logic;
    signal tx_rst_done : std_logic;
    signal txusrpll_locked : std_logic;
    signal rx_rst_done : std_logic;
    signal comma_pos_valid : std_logic;
    signal txresetdone : std_logic;
    signal rxresetdone : std_logic;
    signal lpdc_regs_out : t_lpdc_regs_master_out;
    signal lpdc_regs_in : t_lpdc_regs_master_in;
    signal drp_regs_in : t_wishbone_slave_out;
    signal drp_regs_out : t_wishbone_slave_in;
    begin
    tx_sw_reset <= lpc_ctrl_i(0);
    tx_enable <= lpc_ctrl_i(1); -- Not used. Tx enabled after tx_out_clk synced rst_n
    rx_enable <= lpc_ctrl_i(2); -- Not used. Rx enables after serdes_ready_rxclk
    rx_sw_reset <= lpc_ctrl_i(3);
    cpll_sw_reset <= lpc_ctrl_i(4); -- Not used. cpll reset already incorporated in tx_sw_reset
    cd_reset <= lpc_ctrl_i(5);
    U_LPDC_regs : entity work.lpdc_mdio_regs
    port map (
    rst_n_i => rst_sys_n_i,
    clk_i => clk_sys_i,
    wb_i => mdio_slave_i,
    wb_o => mdio_slave_o,
    lpdc_regs_i => lpdc_regs_in,
    lpdc_regs_o => lpdc_regs_out,
    drp_regs_i => drp_regs_in,
    drp_regs_o => drp_regs_out);
    -- Near-end PMA loopback if loopen_i active
    gth_loopback <= "010" when loopen_i = '1' else "000";
    ......@@ -298,7 +301,7 @@ begin
    (
    clk_i => clk_dmtd_i,
    rst_n_i => '1',
    data_i => tx_sw_reset,
    data_i => lpdc_regs_out.CTRL_tx_sw_reset,
    synced_o => gth_tx_reset_a
    );
    ......@@ -307,7 +310,7 @@ begin
    (
    clk_i => tx_out_clk,
    rst_n_i => '1',
    data_i => tx_enable,
    data_i => lpdc_regs_out.CTRL_tx_enable,
    synced_o => tx_enable_txclk
    );
    ......@@ -316,7 +319,7 @@ begin
    (
    clk_i => clk_dmtd_i,
    rst_n_i => '1',
    data_i => rx_sw_reset,
    data_i => lpdc_regs_out.CTRL_rx_sw_reset,
    synced_o => gth_rx_reset_a
    );
    ......@@ -340,11 +343,9 @@ begin
    clk_dmtd_i => clk_dmtd_i,
    clk_sampled_o => tx_out_clk_sampled);
    comma_target_pos <= lpc_ctrl_i(13 downto 13 - 4);
    process(rx_rec_clk_sampled, tx_out_clk_sampled, lpc_ctrl_i)
    process(rx_rec_clk_sampled, tx_out_clk_sampled, lpdc_regs_out)
    begin
    case lpc_ctrl_i(15 downto 14) is
    case lpdc_regs_out.CTRL_dmtd_clk_sel is
    when "00" =>
    clk_sampled_o <= rx_rec_clk_sampled;
    when "01" =>
    ......@@ -354,8 +355,6 @@ begin
    end case;
    end process;
    tx_enc_err_o <= '0';
    U_SyncReset : gc_sync_ffs
    port map
    (
    ......@@ -512,21 +511,21 @@ begin
    rst_n_i => '1',
    data_i => serdes_ready_a,
    synced_o => serdes_ready_txclk);
    U_Comma_Detect : gtx_comma_detect_lp
    generic map(
    g_id => 0
    )
    port map (
    clk_rx_i => rx_rec_clk,
    rst_i => cd_reset,
    rst_i => lpdc_regs_out.CTRL_aux_reset,
    rx_data_raw_i => rx_data_raw,
    rx_data_raw_o => rx_data_decode,
    comma_target_pos_i => comma_target_pos,
    comma_current_pos_o => comma_current_pos,
    comma_pos_valid_o => comma_pos_valid,
    link_up_o => link_up,
    aligned_o => link_aligned);
    comma_target_pos_i => lpdc_regs_out.CTRL_comma_target_pos(4 downto 0),
    comma_current_pos_o => lpdc_regs_in.STAT_comma_current_pos(4 downto 0),
    comma_pos_valid_o => lpdc_regs_in.STAT_comma_pos_valid,
    link_up_o => lpdc_regs_in.STAT_link_up,
    aligned_o => lpdc_regs_in.STAT_link_aligned);
    U_Sync_RxReset : gc_sync_ffs
    port map (
    ......@@ -555,19 +554,10 @@ begin
    rdisp_err_o => open,
    out_8b_o => rx_data_int(7 downto 0));
    lpc_stat_o(0) <= '1'; -- Not used. Signal cpll_locked
    lpc_stat_o(1) <= link_up;
    lpc_stat_o(2) <= link_aligned;
    lpc_stat_o(3) <= tx_rst_done;
    lpc_stat_o(4) <= '1'; -- Not used. Signal txusrpll_locked
    lpc_stat_o(5) <= rx_rst_done;
    lpc_stat_o(13 downto 9) <= comma_current_pos;
    lpc_stat_o(14) <= comma_pos_valid;
    -- Debug not used:
    lpc_stat_o(6) <= '0';
    lpc_stat_o(15) <= '0';
    lpdc_regs_in.STAT_pll_locked <= '1'; -- Not used. Signal pll_locked
    lpdc_regs_in.STAT_txusrpll_locked <= '1'; -- Not used. Signal pll_locked
    lpdc_regs_in.STAT_tx_rst_done <= tx_rst_done;
    lpdc_regs_in.STAT_rx_rst_done <= rx_rst_done;
    p_gen_rx_outputs : process(rx_rec_clk, rst_rxclk_n)
    begin
    ......
    platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
    View file @ d7c7b52e
    ......@@ -6,7 +6,7 @@
    -- Author : Peter Jansweijer, Tomasz Wlostowski
    -- Company : CERN BE-CO-HT
    -- Created : 2013-04-08
    -- Last update: 2019-07-01
    -- Last update: 2023-08-18
    -- Platform : FPGA-generic
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    ......@@ -39,6 +39,7 @@
    -- 2013-04-08 0.1 PeterJ Initial release based on "wr_gtx_phy_virtex6.vhd"
    -- 2013-08-19 0.2 PeterJ Implemented a small delay before a rx_cdr_lock is propgated
    -- 2014-02_19 0.3 Peterj Added tx_locked_o to indicate that the cpll reached the lock status
    -- 2023-08-18 0.4 PeterJ use WB bus for LPDC regs (resets now under software control)
    -------------------------------------------------------------------------------
    library ieee;
    ......@@ -51,13 +52,14 @@ use unisim.vcomponents.all;
    library work;
    use work.gencores_pkg.all;
    use work.disparity_gen_pkg.all;
    use work.wishbone_pkg.all;
    use work.lpdc_mdio_regs_pkg.all;
    entity wr_gtx_phy_family7_lp is
    generic (
    -- set to non-zero value to speed up the simulation by reducing some delays
    g_simulation : integer := 0;
    g_id : integer := 0
    g_simulation : integer := 0
    );
    port (
    ......@@ -72,6 +74,10 @@ entity wr_gtx_phy_family7_lp is
    -- Reference 125 MHz clock input for the TX/RX deterministic phase logic (not the GTX itself)
    clk_ref_i : in std_logic;
    -- systemc clock for MDIO registers
    clk_sys_i : in std_logic;
    rst_sys_n_i : in std_logic;
    -- TX path, synchronous to tx_out_clk_o (125 MHz):
    tx_out_clk_o : out std_logic;
    tx_locked_o : out std_logic;
    ......@@ -119,6 +125,7 @@ entity wr_gtx_phy_family7_lp is
    rst_i : in std_logic;
    loopen_i : in std_logic;
    tx_prbs_sel_i : in std_logic_vector(2 downto 0);
    pad_txn_o : out std_logic;
    pad_txp_o : out std_logic;
    ......@@ -127,13 +134,12 @@ entity wr_gtx_phy_family7_lp is
    rdy_o : out std_logic;
    lpc_ctrl_i : in std_logic_vector(15 downto 0) := x"0000";
    lpc_stat_o : out std_logic_vector(15 downto 0);
    mdio_slave_i : in t_wishbone_slave_in;
    mdio_slave_o : out t_wishbone_slave_out;
    fmon_clk_tx_o : out std_logic;
    fmon_clk_tx2_o : out std_logic;
    fmon_clk_rx_o : out std_logic
    );
    end wr_gtx_phy_family7_lp;
    ......@@ -149,12 +155,6 @@ architecture rtl of wr_gtx_phy_family7_lp is
    clk_sampled_o : out std_logic);
    end component dmtd_sampler;
    component BUFG
    port (
    O : out std_ulogic;
    I : in std_ulogic);
    end component;
    component gc_dec_8b10b is
    port (
    clk_i : in std_logic;
    ......@@ -166,146 +166,109 @@ architecture rtl of wr_gtx_phy_family7_lp is
    out_8b_o : out std_logic_vector(7 downto 0));
    end component gc_dec_8b10b;
    constant c_rxcdrlock_max : integer := 1000;
    constant c_reset_cnt_max : integer := 64; -- Reset pulse width 64 * 8 = 512 ns
    signal rst_synced : std_logic;
    signal gtx_rst, gtx_rst_n : std_logic;
    signal rst_d0 : std_logic;
    signal reset_counter : unsigned(9 downto 0);
    signal rx_rec_clk_bufin : std_logic;
    signal rx_rec_clk : std_logic;
    signal tx_out_clk_bufin : std_logic;
    signal tx_out_clk : std_logic;
    signal rx_cdr_lock : std_logic;
    signal rx_cdr_lock_filtered : std_logic;
    signal tx_rst_done, rx_rst_done : std_logic;
    signal txpll_lockdet, rxpll_lockdet : std_logic;
    -- signal pll_lockdet : std_logic;
    signal cpll_locked : std_logic;
    signal everything_ready : std_logic;
    signal rst_done : std_logic;
    signal rst_done_n : std_logic;
    signal rx_k_o_int : std_logic_vector(1 downto 0);
    signal rx_data_o_int : std_logic_vector(15 downto 0);
    signal rx_k_int : std_logic_vector(1 downto 0);
    signal rx_data_int : std_logic_vector(15 downto 0);
    signal rx_data_wrap : std_logic_vector(15 downto 0);
    signal rx_charisk_wrap : std_logic_vector(1 downto 0);
    signal rx_disperr_wrap : std_logic_vector(1 downto 0);
    signal rx_data_raw : std_logic_vector(19 downto 0);
    signal rx_data_decode : std_logic_vector(19 downto 0);
    signal rx_enc_err_o_int : std_logic;
    signal rx_disp_err, rx_code_err : std_logic_vector(1 downto 0);
    signal tx_is_k_swapped : std_logic_vector(1 downto 0);
    signal tx_data_swapped : std_logic_vector(15 downto 0);
    signal tx_data_synced : std_logic_vector(15 downto 0);
    signal tx_k_synced : std_logic_vector(1 downto 0);
    component gtx_comma_detect_lp is
    generic (
    g_ID : integer);
    port (
    clk_rx_i : in std_logic;
    rst_i : in std_logic;
    rx_data_raw_i : in std_logic_vector(19 downto 0);
    rx_data_raw_o : out std_logic_vector(19 downto 0);
    comma_target_pos_i : in std_logic_vector(4 downto 0);
    comma_current_pos_o : out std_logic_vector(4 downto 0);
    comma_pos_valid_o : out std_logic;
    link_up_o : out std_logic;
    aligned_o : out std_logic);
    end component gtx_comma_detect_lp;
    signal rst_n : std_logic;
    signal cur_disp : t_8b10b_disparity;
    signal tx_out_clk : std_logic;
    signal tx_out_clk_sampled : std_logic;
    signal rx_rec_clk : std_logic;
    signal rx_rec_clk_sampled : std_logic;
    signal rx_rec_clk_bufin : std_logic;
    signal tx_out_clk_bufin : std_logic;
    signal link_up, link_aligned : std_logic;
    signal tx_enable, tx_enable_txclk : std_logic;
    signal serdes_ready_a : std_logic;
    signal serdes_ready_txclk : std_logic;
    signal serdes_ready_rxclk : std_logic;
    signal tx_sw_reset : std_logic;
    signal rx_enable, rx_enable_rxclk : std_logic;
    signal gtx_rx_reset_a : std_logic;
    signal gtx_tx_reset_a : std_logic;
    signal cpll_reset_a : std_logic;
    signal rst_txclk_n : std_logic;
    signal rst_rxclk_n : std_logic;
    signal rx_sw_reset : std_logic;
    signal rx_rec_clk_sampled, tx_out_clk_sampled : std_logic;
    signal gtx_loopback : std_logic_vector(2 downto 0);
    signal cpll_reset_a : std_logic;
    signal cpll_locked : std_logic;
    signal tx_data_8b10b : std_logic_vector(19 downto 0);
    signal tx_data_synced : std_logic_vector(15 downto 0);
    signal tx_k_synced : std_logic_vector(1 downto 0);
    signal run_disparity_q0 : std_logic;
    signal run_disparity_q1 : std_logic;
    signal run_disparity_reg : std_logic;
    function f_widen(x : std_logic_vector; ratio : integer) return std_logic_vector is
    variable rv : std_logic_vector(x'length * ratio -1 downto 0);
    begin
    for i in 0 to x'length-1 loop
    rv(i*ratio + ratio-1 downto i*ratio) := (others => x(i));
    end loop;
    signal rx_data_int : std_logic_vector(19 downto 0);
    signal rx_k_int : std_logic_vector(1 downto 0);
    attribute keep : string;
    attribute keep of rx_data_int : signal is "true";
    attribute keep of rx_k_int : signal is "true";
    return rv;
    end function;
    signal cur_disp : t_8b10b_disparity;
    signal tx_data_8b10b : std_logic_vector(19 downto 0);
    signal comma_target_pos : std_logic_vector(4 downto 0);
    signal comma_current_pos : std_logic_vector(4 downto 0);
    signal comma_pos_valid : std_logic;
    signal tx_enable_txclk : std_logic;
    signal tx_out_clk_div2 : std_logic;
    signal tx_out_clk_div1 : std_logic;
    signal gtx_rst_n_txdiv2 : std_logic;
    signal gtx_tx_reset_a : std_logic;
    signal gtx_rx_reset_a : std_logic;
    signal run_disparity_q0, run_disparity_q1 : std_logic;
    signal run_disparity_reg : std_logic;
    signal gtx_loopback : std_logic_vector(2 downto 0);
    signal tx_out_clk_div1_bufin : std_logic;
    signal txusrpll_locked : std_logic;
    signal rx_data_raw : std_logic_vector(19 downto 0);
    signal rx_data_decode : std_logic_vector(19 downto 0);
    signal rx_code_err : std_logic_vector(1 downto 0);
    signal cpll_sw_reset : std_logic;
    signal cd_reset : std_logic;
    signal tx_rst_done : std_logic;
    signal txusrpll_locked : std_logic;
    signal rx_rst_done : std_logic;
    attribute mark_debug : string;
    attribute mark_debug of rx_data_raw : signal is "true";
    attribute mark_debug of tx_data_i : signal is "true";
    attribute mark_debug of tx_k_i : signal is "true";
    attribute mark_debug of rx_k_int : signal is "true";
    attribute mark_debug of rx_data_int : signal is "true";
    attribute mark_debug of link_up : signal is "true";
    attribute mark_debug of link_aligned : signal is "true";
    attribute mark_debug of tx_sw_reset : signal is "true";
    attribute mark_debug of rx_sw_reset : signal is "true";
    attribute mark_debug of tx_enable : signal is "true";
    attribute mark_debug of rx_enable: signal is "true";
    signal lpdc_regs_out : t_lpdc_regs_master_out;
    signal lpdc_regs_in : t_lpdc_regs_master_in;
    signal drp_regs_in : t_wishbone_slave_out;
    signal drp_regs_out : t_wishbone_slave_in;
    begin -- rtl
    begin
    tx_sw_reset <= lpc_ctrl_i(0);
    tx_enable <= lpc_ctrl_i(1);
    rx_enable <= lpc_ctrl_i(2);
    rx_sw_reset <= lpc_ctrl_i(3);
    cpll_sw_reset <= lpc_ctrl_i(4);
    cd_reset <= lpc_ctrl_i(5);
    U_LPDC_regs : entity work.lpdc_mdio_regs
    port map (
    rst_n_i => rst_sys_n_i,
    clk_i => clk_sys_i,
    wb_i => mdio_slave_i,
    wb_o => mdio_slave_o,
    lpdc_regs_i => lpdc_regs_in,
    lpdc_regs_o => lpdc_regs_out,
    drp_regs_i => drp_regs_in,
    drp_regs_o => drp_regs_out);
    -- Near-end PMA loopback if loopen_i active
    gtx_loopback <= "010" when loopen_i = '1' else "000";
    U_SyncTxEnable : gc_sync_ffs
    U_SyncTxReset : gc_sync_ffs
    port map
    (
    clk_i => tx_out_clk_div2,
    clk_i => clk_dmtd_i,
    rst_n_i => '1',
    data_i => tx_enable,
    synced_o => tx_enable_txclk
    );
    U_SyncTxUsrcCLK2Reset : gc_sync_ffs
    port map
    (
    clk_i => tx_out_clk_div2,
    rst_n_i => gtx_rst_n,
    data_i => '1',
    synced_o => gtx_rst_n_txdiv2
    data_i => lpdc_regs_out.CTRL_tx_sw_reset,
    synced_o => gtx_tx_reset_a
    );
    U_SyncRxEnable : gc_sync_ffs
    U_SyncTxEnable : gc_sync_ffs
    port map
    (
    clk_i => rx_rec_clk,
    clk_i => tx_out_clk,
    rst_n_i => '1',
    data_i => rx_enable,
    synced_o => rx_enable_rxclk
    data_i => lpdc_regs_out.CTRL_tx_enable,
    synced_o => tx_enable_txclk
    );
    U_SyncRxReset : gc_sync_ffs
    ......@@ -313,7 +276,7 @@ begin -- rtl
    (
    clk_i => clk_dmtd_i,
    rst_n_i => '1',
    data_i => rx_sw_reset,
    data_i => lpdc_regs_out.CTRL_rx_sw_reset,
    synced_o => gtx_rx_reset_a
    );
    ......@@ -322,18 +285,11 @@ begin -- rtl
    (
    clk_i => clk_dmtd_i,
    rst_n_i => '1',
    data_i => cpll_sw_reset,
    data_i => lpdc_regs_out.CTRL_pll_sw_reset,
    synced_o => cpll_reset_a
    );
    U_SyncTxReset : gc_sync_ffs
    port map
    (
    clk_i => clk_dmtd_i,
    rst_n_i => '1',
    data_i => tx_sw_reset,
    synced_o => gtx_tx_reset_a
    );
    rst_n <= not rst_i;
    U_Sampler_RX : dmtd_sampler
    generic map (
    ......@@ -349,16 +305,13 @@ begin -- rtl
    g_divide_input_by_2 => false,
    g_reverse => true)
    port map (
    clk_in_i => tx_out_clk_div2,
    clk_in_i => tx_out_clk,
    clk_dmtd_i => clk_dmtd_i,
    clk_sampled_o => tx_out_clk_sampled);
    comma_target_pos <= lpc_ctrl_i(13 downto 13 - 4);
    process(rx_rec_clk_sampled, tx_out_clk_sampled, lpc_ctrl_i)
    process(rx_rec_clk_sampled, tx_out_clk_sampled, lpdc_regs_out)
    begin
    case lpc_ctrl_i(15 downto 14) is
    case lpdc_regs_out.CTRL_dmtd_clk_sel is
    when "00" =>
    clk_sampled_o <= rx_rec_clk_sampled;
    when "01" =>
    ......@@ -368,29 +321,13 @@ begin -- rtl
    end case;
    end process;
    tx_enc_err_o <= '0';
    p_gen_reset : process(clk_ref_i)
    begin
    if rising_edge(clk_ref_i) then
    rst_d0 <= rst_i;
    rst_synced <= rst_d0;
    if(rst_synced = '1') then
    reset_counter <= (others => '0');
    else
    if(reset_counter(reset_counter'left) = '0') then
    reset_counter <= reset_counter + 1;
    end if;
    end if;
    end if;
    end process;
    gtx_rst <= rst_synced or std_logic(not reset_counter(reset_counter'left));
    tx_out_clk_o <= tx_out_clk_div2;
    tx_locked_o <= cpll_locked;
    U_SyncReset : gc_sync_ffs
    port map
    (
    clk_i => tx_out_clk,
    rst_n_i => '1',
    data_i => rst_n,
    synced_o => rst_txclk_n);
    U_BUF_RxRecClk : BUFG
    port map (
    ......@@ -399,9 +336,9 @@ begin -- rtl
    rx_rbclk_o <= rx_rec_clk;
    -- clk_ref_i and tx_out_clk_div2 are phase locked but can have an offset.
    -- clk_ref_i and tx_out_clk are phase locked but can have an offset.
    -- As a safety precaustion, resynchronize clk_ref_i domain signals tx_data_i and tx_k_i
    -- into the tx_out_clk_div2 domain.
    -- into the tx_out_clk domain.
    U_SyncTxData : gc_sync_register
    generic map
    (
    ......@@ -409,8 +346,8 @@ begin -- rtl
    )
    port map
    (
    clk_i => tx_out_clk_div2,
    rst_n_a_i => gtx_rst_n_txdiv2,
    clk_i => tx_out_clk,
    rst_n_a_i => rst_txclk_n,
    d_i => tx_data_i,
    q_o => tx_data_synced
    );
    ......@@ -422,8 +359,8 @@ begin -- rtl
    )
    port map
    (
    clk_i => tx_out_clk_div2,
    rst_n_a_i => gtx_rst_n_txdiv2,
    clk_i => tx_out_clk,
    rst_n_a_i => rst_txclk_n,
    d_i => tx_k_i,
    q_o => tx_k_synced
    );
    ......@@ -434,8 +371,8 @@ begin -- rtl
    g_use_internal_running_disparity => false
    )
    port map (
    clk_i => tx_out_clk_div2,
    rst_n_i => gtx_rst_n_txdiv2,
    clk_i => tx_out_clk,
    rst_n_i => rst_txclk_n,
    in_8b_i => tx_data_synced(15 downto 8),
    dispar_i => run_disparity_reg,
    dispar_o => run_disparity_q0,
    ......@@ -447,19 +384,19 @@ begin -- rtl
    g_use_internal_running_disparity => false
    )
    port map (
    clk_i => tx_out_clk_div2,
    rst_n_i => gtx_rst_n_txdiv2,
    clk_i => tx_out_clk,
    rst_n_i => rst_txclk_n,
    dispar_i => run_disparity_q0,
    dispar_o => run_disparity_q1,
    in_8b_i => tx_data_synced(7 downto 0),
    ctrl_i => tx_k_synced(0),
    out_10b_o => tx_data_8b10b(19 downto 10));
    p_latch_disparity : process(tx_out_clk_div2)
    p_latch_disparity : process(tx_out_clk)
    begin
    if rising_edge(tx_out_clk_div2) then
    if gtx_rst_n_txdiv2 = '0' then
    if rising_edge(tx_out_clk) then
    if rst_txclk_n = '0' then
    run_disparity_reg <= '0';
    else
    run_disparity_reg <= run_disparity_q1;
    ......@@ -468,20 +405,6 @@ begin -- rtl
    end if;
    end process;
    -- U_QPLL_INST : entity work.wr_gtx_phy_family7_lp_qpll
    -- generic map
    -- (
    -- g_simulation => g_simulation
    -- )
    -- port map
    -- (
    -- rst_i => qpll_reset_a,
    -- clk_gtx_i => clk_gtx_i,
    -- qpll_clk_o => qpll_clk,
    -- qpll_ref_clk_o => qpll_ref_clk,
    -- locked_o => qpll_locked
    -- );
    U_GTX_INST : entity work.whiterabbit_gtxe2_channel_wrapper_GT_lp
    generic map
    (
    ......@@ -512,13 +435,12 @@ begin -- rtl
    ------------------------------- Loopback Ports -----------------------------
    LOOPBACK_IN => gtx_loopback,
    --------------------- RX Initialization and Reset Ports --------------------
    -- RXUSERRDY_IN => rx_cdr_lock,
    RXUSERRDY_IN => '1', --rx_cdr_lock_filtered,
    RXUSERRDY_IN => '1',
    -------------------------- RX Margin Analysis Ports ------------------------
    EYESCANDATAERROR_OUT => open,
    ------------------------- Receive Ports - CDR Ports ------------------------
    RXCDRLOCK_OUT => rx_cdr_lock,
    RXCDRRESET_IN => '0', -- this port cannot be generated by the CoreGen GUI, it cannot be turnes "on" : in std_logic;
    RXCDRLOCK_OUT => open,
    RXCDRRESET_IN => '0', -- this port cannot be generated by the CoreGen GUI, it cannot be turned "on" : in std_logic;
    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
    RXUSRCLK_IN => rx_rec_clk,
    RXUSRCLK2_IN => rx_rec_clk,
    ......@@ -545,7 +467,6 @@ begin -- rtl
    TXUSRCLK_IN => tx_out_clk,
    TXUSRCLK2_IN => tx_out_clk,
    ------------------ Transmit Ports - TX Data Path interface -----------------
    --TXDATA_IN => f_widen(tx_data_8b10b, 1),
    TXDATA_IN => tx_data_8b10b,
    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
    GTXTXN_OUT => pad_txn_o,
    ......@@ -560,72 +481,55 @@ begin -- rtl
    TXPRBSSEL_IN => "000" --tx_prbs_sel_i
    );
    txusrpll_locked <= '1';
    tx_out_clk_div2 <= tx_out_clk;
    U_BUF_TxOutClk : BUFG
    port map (
    I => tx_out_clk_bufin,
    O => tx_out_clk);
    --U_BUF_TxOutClkFB : BUFG
    -- port map (
    -- I => pll_clkfbout_bufin,
    -- O => pll_clkfbout);
    txpll_lockdet <= cpll_locked;
    rxpll_lockdet <= rx_cdr_lock_filtered;
    rst_done <= rx_rst_done and tx_rst_done;
    rst_done_n <= not rst_done;
    everything_ready <= rst_done and txpll_lockdet and rxpll_lockdet;
    rdy_o <= everything_ready;
    -- 2013 August 19: Peterj
    -- The family 7 GTX seem to have an artifact in rx_cdr_lock. For no reason lock may be lost for a clock cycle
    -- There is not much information on the web but examples of "Series-7 Integrated Block for PCI Express" (pipe_user.v)
    -- show that Xilinx itself implements a small delay before an rx_cdr_lock is propagated.
    p_rx_cdr_lock_filter : process(rx_rec_clk, gtx_rst)
    variable rxcdrlock_cnt : integer range 0 to c_rxcdrlock_max;
    begin
    if(gtx_rst = '1') then
    rxcdrlock_cnt := 0;
    rx_cdr_lock_filtered <= '0';
    elsif rising_edge(rx_rec_clk) then
    if rx_cdr_lock = '0' then
    if rxcdrlock_cnt /= c_rxcdrlock_max then
    rxcdrlock_cnt := rxcdrlock_cnt + 1;
    else
    rx_cdr_lock_filtered <= '0';
    end if;
    else
    rxcdrlock_cnt := 0;
    rx_cdr_lock_filtered <= '1';
    end if;
    end if;
    end process;
    tx_out_clk_o <= tx_out_clk;
    serdes_ready_a <= rst_n and tx_rst_done and rx_rst_done;
    U_Sync_Serdes_RDY1 : gc_sync_ffs
    port map (
    clk_i => rx_rec_clk,
    rst_n_i => '1',
    data_i => serdes_ready_a,
    synced_o => serdes_ready_rxclk);
    U_Sync_Serdes_RDY2 : gc_sync_ffs
    port map (
    clk_i => tx_out_clk,
    rst_n_i => '1',
    data_i => serdes_ready_a,
    synced_o => serdes_ready_txclk);
    U_Comma_Detect : entity work.gtx_comma_detect_lp
    U_Comma_Detect : gtx_comma_detect_lp
    generic map(
    g_id => g_id
    g_id => 0
    )
    port map (
    clk_rx_i => rx_rec_clk,
    rst_i => cd_reset,
    rx_data_raw_i => rx_data_raw,
    rx_data_raw_o => rx_data_decode,
    comma_target_pos_i => comma_target_pos,
    comma_current_pos_o => comma_current_pos,
    comma_pos_valid_o => comma_pos_valid,
    link_up_o => link_up,
    aligned_o => link_aligned);
    gtx_rst_n <= not gtx_rst;
    clk_rx_i => rx_rec_clk,
    rst_i => lpdc_regs_out.CTRL_aux_reset,
    rx_data_raw_i => rx_data_raw,
    rx_data_raw_o => rx_data_decode,
    comma_target_pos_i => lpdc_regs_out.CTRL_comma_target_pos(4 downto 0),
    comma_current_pos_o => lpdc_regs_in.STAT_comma_current_pos(4 downto 0),
    comma_pos_valid_o => lpdc_regs_in.STAT_comma_pos_valid,
    link_up_o => lpdc_regs_in.STAT_link_up,
    aligned_o => lpdc_regs_in.STAT_link_aligned);
    U_Sync_RxReset : gc_sync_ffs
    port map (
    clk_i => rx_rec_clk,
    rst_n_i => '1',
    data_i => rst_n,
    synced_o => rst_rxclk_n);
    U_Dec1 : gc_dec_8b10b
    port map (
    clk_i => rx_rec_clk,
    rst_n_i => gtx_rst_n,
    rst_n_i => rst_rxclk_n,
    in_10b_i => (rx_data_decode(19 downto 10)),
    ctrl_o => rx_k_int(1),
    code_err_o => rx_code_err(1),
    ......@@ -635,51 +539,41 @@ begin -- rtl
    U_Dec2 : gc_dec_8b10b
    port map (
    clk_i => rx_rec_clk,
    rst_n_i => gtx_rst_n,
    rst_n_i => rst_rxclk_n,
    in_10b_i => (rx_data_decode(9 downto 0)),
    ctrl_o => rx_k_int(0),
    code_err_o => rx_code_err(0),
    rdisp_err_o => open,
    out_8b_o => rx_data_int(7 downto 0));
    rx_disp_err <= (others => '0');
    lpc_stat_o(0) <= cpll_locked;
    lpc_stat_o(1) <= link_up;
    lpc_stat_o(2) <= link_aligned;
    lpc_stat_o(3) <= tx_rst_done;
    lpc_stat_o(4) <= txusrpll_locked;
    lpc_stat_o(5) <= rx_rst_done;
    lpdc_regs_in.STAT_pll_locked <= cpll_locked;
    lpdc_regs_in.STAT_txusrpll_locked <= '1'; -- Not used. Signal pll_locked
    lpdc_regs_in.STAT_tx_rst_done <= tx_rst_done;
    lpdc_regs_in.STAT_rx_rst_done <= rx_rst_done;
    lpc_stat_o(13 downto 9) <= comma_current_pos;
    lpc_stat_o(14) <= comma_pos_valid;
    -- Debug not used:
    lpc_stat_o(6) <= '0';
    lpc_stat_o(15) <= '0';
    p_gen_rx_outputs : process(rx_rec_clk, gtx_rst)
    p_gen_rx_outputs : process(rx_rec_clk, rst_rxclk_n)
    begin
    if(gtx_rst = '1') then
    rx_data_o_int <= (others => '0');
    rx_k_o_int <= (others => '0');
    rx_enc_err_o_int <= '0';
    if(rst_rxclk_n = '0') then
    rx_data_o <= (others => '0');
    rx_k_o <= (others => '0');
    rx_enc_err_o <= '0';
    elsif rising_edge(rx_rec_clk) then
    if(rx_enable_rxclk = '1') then
    rx_data_o_int <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
    rx_k_o_int <= rx_k_int(0) & rx_k_int(1);
    rx_enc_err_o_int <= rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
    if(serdes_ready_rxclk = '1') then
    rx_data_o <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
    rx_k_o <= rx_k_int(0) & rx_k_int(1);
    rx_enc_err_o <= rx_code_err(0) or rx_code_err(1);
    else
    rx_data_o_int <= (others => '1');
    rx_k_o_int <= (others => '1');
    rx_enc_err_o_int <= '1';
    rx_data_o <= (others => '1');
    rx_k_o <= (others => '1');
    rx_enc_err_o <= '1';
    end if;
    end if;
    end process;
    p_gen_tx_disparity : process(tx_out_clk_div2)
    p_gen_tx_disparity : process(tx_out_clk)
    begin
    if rising_edge(tx_out_clk_div2) then
    if rising_edge(tx_out_clk) then
    -- synchronously enable calculation of tuning disparity
    if tx_enable_txclk = '0' then
    cur_disp <= RD_MINUS;
    else
    ......@@ -690,14 +584,14 @@ begin -- rtl
    tx_disparity_o <= to_std_logic(cur_disp);
    rx_data_o <= rx_data_o_int;
    rx_k_o <= rx_k_o_int;
    rx_enc_err_o <= rx_enc_err_o_int;
    fmon_clk_tx_o <= tx_out_clk_div1;
    fmon_clk_tx2_o <= tx_out_clk_div2;
    fmon_clk_tx_o <= tx_out_clk;
    fmon_clk_tx2_o <= tx_out_clk;
    fmon_clk_rx_o <= rx_rec_clk;
    rx_bitslide_o <= (others => '0');
    rdy_o <= serdes_ready_rxclk;
    tx_locked_o <= cpll_locked;
    tx_enc_err_o <= '0';
    end rtl;
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2.v 0 → 100644
    View file @ d7c7b52e
    // (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //
    // DO NOT MODIFY THIS FILE.
    // IP VLNV: xilinx.com:ip:gtwizard_ultrascale:1.7
    // IP Revision: 13
    (* X_CORE_INFO = "gtwizard_ultrascale_2_gtwizard_top,Vivado 2022.1" *)
    (* CHECK_LICENSE_TYPE = "gtwizard_ultrascale_2,gtwizard_ultrascale_2_gtwizard_top,{}" *)
    (* CORE_GENERATION_INFO = "gtwizard_ultrascale_2,gtwizard_ultrascale_2_gtwizard_top,{x_ipProduct=Vivado 2022.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=gtwizard_ultrascale,x_ipVersion=1.7,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_CHANNEL_ENABLE=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001,C_PCIE_ENABLE=0,C_PCIE_CORECLK_FREQ=250,C_COMMON_SCALING_FACTOR=\
    1,C_CPLL_VCO_FREQUENCY=2500.0,C_FORCE_COMMONS=0,C_FREERUN_FREQUENCY=62.5,C_GT_TYPE=2,C_GT_REV=57,C_INCLUDE_CPLL_CAL=2,C_ENABLE_COMMON_USRCLK=0,C_USER_GTPOWERGOOD_DELAY_EN=1,C_SIM_CPLL_CAL_BYPASS=1,C_LOCATE_COMMON=0,C_LOCATE_RESET_CONTROLLER=0,C_LOCATE_USER_DATA_WIDTH_SIZING=0,C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_IN_SYSTEM_IBERT_CORE=1,C_LOCATE_RX_USER_CLOCKING=0,C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_TX_USER_CLOCKING=0,C_RESET_CONTROLLER_INSTANCE_CTRL=0,C_RX_BUFFBYPASS_MODE=0\
    ,C_RX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_RX_BUFFER_MODE=0,C_RX_CB_DISP=00000000,C_RX_CB_K=00000000,C_RX_CB_MAX_LEVEL=1,C_RX_CB_LEN_SEQ=1,C_RX_CB_NUM_SEQ=0,C_RX_CB_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_CC_DISP=00000000,C_RX_CC_ENABLE=0,C_RESET_SEQUENCE_INTERVAL=0,C_RX_CC_K=00000000,C_RX_CC_LEN_SEQ=1,C_RX_CC_NUM_SEQ=0,C_RX_CC_PERIODICITY=5000,C_RX_CC_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_COMMA_M_EN\
    ABLE=0,C_RX_COMMA_M_VAL=1010000011,C_RX_COMMA_P_ENABLE=0,C_RX_COMMA_P_VAL=0101111100,C_RX_DATA_DECODING=0,C_RX_ENABLE=1,C_RX_INT_DATA_WIDTH=20,C_RX_LINE_RATE=1.25,C_RX_MASTER_CHANNEL_IDX=0,C_RX_OUTCLK_BUFG_GT_DIV=1,C_RX_OUTCLK_FREQUENCY=62.5000000,C_RX_OUTCLK_SOURCE=1,C_RX_PLL_TYPE=2,C_RX_RECCLK_OUTPUT=0x000000000000000000000000000000000000000000000000,C_RX_REFCLK_FREQUENCY=100,C_RX_SLIDE_MODE=1,C_RX_USER_CLOCKING_CONTENTS=0,C_RX_USER_CLOCKING_INSTANCE_CTRL=0,C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCL\
    K=1,C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_RX_USER_CLOCKING_SOURCE=0,C_RX_USER_DATA_WIDTH=20,C_RX_USRCLK_FREQUENCY=62.5000000,C_RX_USRCLK2_FREQUENCY=62.5000000,C_SECONDARY_QPLL_ENABLE=0,C_SECONDARY_QPLL_REFCLK_FREQUENCY=257.8125,C_TOTAL_NUM_CHANNELS=1,C_TOTAL_NUM_COMMONS=0,C_TOTAL_NUM_COMMONS_EXAMPLE=0,C_TXPROGDIV_FREQ_ENABLE=0,C_TXPROGDIV_FREQ_SOURCE=2,C_TXPROGDIV_FREQ_VAL=62.5,C_TX_BUFFBYPASS_MODE=0,C_TX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_TX_BUFFER_MODE=0,C_TX_DATA_ENCODING=0,C_TX_ENABLE=1\
    ,C_TX_INT_DATA_WIDTH=20,C_TX_LINE_RATE=1.25,C_TX_MASTER_CHANNEL_IDX=0,C_TX_OUTCLK_BUFG_GT_DIV=1,C_TX_OUTCLK_FREQUENCY=62.5000000,C_TX_OUTCLK_SOURCE=4,C_TX_PLL_TYPE=2,C_TX_REFCLK_FREQUENCY=100,C_TX_USER_CLOCKING_CONTENTS=0,C_TX_USER_CLOCKING_INSTANCE_CTRL=0,C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=1,C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_TX_USER_CLOCKING_SOURCE=0,C_TX_USER_DATA_WIDTH=20,C_TX_USRCLK_FREQUENCY=62.5000000,C_TX_USRCLK2_FREQUENCY=62.5000000}" *)
    (* DowngradeIPIdentifiedWarnings = "yes" *)
    module gtwizard_ultrascale_2 (
    gtwiz_userclk_tx_reset_in,
    gtwiz_userclk_tx_srcclk_out,
    gtwiz_userclk_tx_usrclk_out,
    gtwiz_userclk_tx_usrclk2_out,
    gtwiz_userclk_tx_active_out,
    gtwiz_userclk_rx_reset_in,
    gtwiz_userclk_rx_srcclk_out,
    gtwiz_userclk_rx_usrclk_out,
    gtwiz_userclk_rx_usrclk2_out,
    gtwiz_userclk_rx_active_out,
    gtwiz_buffbypass_tx_reset_in,
    gtwiz_buffbypass_tx_start_user_in,
    gtwiz_buffbypass_tx_done_out,
    gtwiz_buffbypass_tx_error_out,
    gtwiz_buffbypass_rx_reset_in,
    gtwiz_buffbypass_rx_start_user_in,
    gtwiz_buffbypass_rx_done_out,
    gtwiz_buffbypass_rx_error_out,
    gtwiz_reset_clk_freerun_in,
    gtwiz_reset_all_in,
    gtwiz_reset_tx_pll_and_datapath_in,
    gtwiz_reset_tx_datapath_in,
    gtwiz_reset_rx_pll_and_datapath_in,
    gtwiz_reset_rx_datapath_in,
    gtwiz_reset_rx_cdr_stable_out,
    gtwiz_reset_tx_done_out,
    gtwiz_reset_rx_done_out,
    gtwiz_userdata_tx_in,
    gtwiz_userdata_rx_out,
    cpllrefclksel_in,
    drpaddr_in,
    drpclk_in,
    drpdi_in,
    drpen_in,
    drpwe_in,
    eyescanreset_in,
    gthrxn_in,
    gthrxp_in,
    gtrefclk0_in,
    loopback_in,
    rxlpmen_in,
    rxrate_in,
    rxslide_in,
    txdiffctrl_in,
    txpostcursor_in,
    txprecursor_in,
    drpdo_out,
    drprdy_out,
    gthtxn_out,
    gthtxp_out,
    gtpowergood_out,
    rxpmaresetdone_out,
    rxresetdone_out,
    txpmaresetdone_out,
    txprgdivresetdone_out,
    txresetdone_out
    );
    input wire [0 : 0] gtwiz_userclk_tx_reset_in;
    output wire [0 : 0] gtwiz_userclk_tx_srcclk_out;
    output wire [0 : 0] gtwiz_userclk_tx_usrclk_out;
    output wire [0 : 0] gtwiz_userclk_tx_usrclk2_out;
    output wire [0 : 0] gtwiz_userclk_tx_active_out;
    input wire [0 : 0] gtwiz_userclk_rx_reset_in;
    output wire [0 : 0] gtwiz_userclk_rx_srcclk_out;
    output wire [0 : 0] gtwiz_userclk_rx_usrclk_out;
    output wire [0 : 0] gtwiz_userclk_rx_usrclk2_out;
    output wire [0 : 0] gtwiz_userclk_rx_active_out;
    input wire [0 : 0] gtwiz_buffbypass_tx_reset_in;
    input wire [0 : 0] gtwiz_buffbypass_tx_start_user_in;
    output wire [0 : 0] gtwiz_buffbypass_tx_done_out;
    output wire [0 : 0] gtwiz_buffbypass_tx_error_out;
    input wire [0 : 0] gtwiz_buffbypass_rx_reset_in;
    input wire [0 : 0] gtwiz_buffbypass_rx_start_user_in;
    output wire [0 : 0] gtwiz_buffbypass_rx_done_out;
    output wire [0 : 0] gtwiz_buffbypass_rx_error_out;
    input wire [0 : 0] gtwiz_reset_clk_freerun_in;
    input wire [0 : 0] gtwiz_reset_all_in;
    input wire [0 : 0] gtwiz_reset_tx_pll_and_datapath_in;
    input wire [0 : 0] gtwiz_reset_tx_datapath_in;
    input wire [0 : 0] gtwiz_reset_rx_pll_and_datapath_in;
    input wire [0 : 0] gtwiz_reset_rx_datapath_in;
    output wire [0 : 0] gtwiz_reset_rx_cdr_stable_out;
    output wire [0 : 0] gtwiz_reset_tx_done_out;
    output wire [0 : 0] gtwiz_reset_rx_done_out;
    input wire [19 : 0] gtwiz_userdata_tx_in;
    output wire [19 : 0] gtwiz_userdata_rx_out;
    input wire [2 : 0] cpllrefclksel_in;
    input wire [9 : 0] drpaddr_in;
    input wire [0 : 0] drpclk_in;
    input wire [15 : 0] drpdi_in;
    input wire [0 : 0] drpen_in;
    input wire [0 : 0] drpwe_in;
    input wire [0 : 0] eyescanreset_in;
    input wire [0 : 0] gthrxn_in;
    input wire [0 : 0] gthrxp_in;
    input wire [0 : 0] gtrefclk0_in;
    input wire [2 : 0] loopback_in;
    input wire [0 : 0] rxlpmen_in;
    input wire [2 : 0] rxrate_in;
    input wire [0 : 0] rxslide_in;
    input wire [4 : 0] txdiffctrl_in;
    input wire [4 : 0] txpostcursor_in;
    input wire [4 : 0] txprecursor_in;
    output wire [15 : 0] drpdo_out;
    output wire [0 : 0] drprdy_out;
    output wire [0 : 0] gthtxn_out;
    output wire [0 : 0] gthtxp_out;
    output wire [0 : 0] gtpowergood_out;
    output wire [0 : 0] rxpmaresetdone_out;
    output wire [0 : 0] rxresetdone_out;
    output wire [0 : 0] txpmaresetdone_out;
    output wire [0 : 0] txprgdivresetdone_out;
    output wire [0 : 0] txresetdone_out;
    gtwizard_ultrascale_2_gtwizard_top #(
    .C_CHANNEL_ENABLE(192'B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001),
    .C_PCIE_ENABLE(0),
    .C_PCIE_CORECLK_FREQ(250),
    .C_COMMON_SCALING_FACTOR(1),
    .C_CPLL_VCO_FREQUENCY(2500.0),
    .C_FORCE_COMMONS(0),
    .C_FREERUN_FREQUENCY(62.5),
    .C_GT_TYPE(2),
    .C_GT_REV(57),
    .C_INCLUDE_CPLL_CAL(2),
    .C_ENABLE_COMMON_USRCLK(0),
    .C_USER_GTPOWERGOOD_DELAY_EN(1),
    .C_SIM_CPLL_CAL_BYPASS(1),
    .C_LOCATE_COMMON(0),
    .C_LOCATE_RESET_CONTROLLER(0),
    .C_LOCATE_USER_DATA_WIDTH_SIZING(0),
    .C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER(0),
    .C_LOCATE_IN_SYSTEM_IBERT_CORE(1),
    .C_LOCATE_RX_USER_CLOCKING(0),
    .C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER(0),
    .C_LOCATE_TX_USER_CLOCKING(0),
    .C_RESET_CONTROLLER_INSTANCE_CTRL(0),
    .C_RX_BUFFBYPASS_MODE(0),
    .C_RX_BUFFER_BYPASS_INSTANCE_CTRL(0),
    .C_RX_BUFFER_MODE(0),
    .C_RX_CB_DISP(8'B00000000),
    .C_RX_CB_K(8'B00000000),
    .C_RX_CB_MAX_LEVEL(1),
    .C_RX_CB_LEN_SEQ(1),
    .C_RX_CB_NUM_SEQ(0),
    .C_RX_CB_VAL(80'B00000000000000000000000000000000000000000000000000000000000000000000000000000000),
    .C_RX_CC_DISP(8'B00000000),
    .C_RX_CC_ENABLE(0),
    .C_RESET_SEQUENCE_INTERVAL(0),
    .C_RX_CC_K(8'B00000000),
    .C_RX_CC_LEN_SEQ(1),
    .C_RX_CC_NUM_SEQ(0),
    .C_RX_CC_PERIODICITY(5000),
    .C_RX_CC_VAL(80'B00000000000000000000000000000000000000000000000000000000000000000000000000000000),
    .C_RX_COMMA_M_ENABLE(0),
    .C_RX_COMMA_M_VAL(10'B1010000011),
    .C_RX_COMMA_P_ENABLE(0),
    .C_RX_COMMA_P_VAL(10'B0101111100),
    .C_RX_DATA_DECODING(0),
    .C_RX_ENABLE(1),
    .C_RX_INT_DATA_WIDTH(20),
    .C_RX_LINE_RATE(1.25),
    .C_RX_MASTER_CHANNEL_IDX(0),
    .C_RX_OUTCLK_BUFG_GT_DIV(1),
    .C_RX_OUTCLK_FREQUENCY(62.5000000),
    .C_RX_OUTCLK_SOURCE(1),
    .C_RX_PLL_TYPE(2),
    .C_RX_RECCLK_OUTPUT(192'H000000000000000000000000000000000000000000000000),
    .C_RX_REFCLK_FREQUENCY(100),
    .C_RX_SLIDE_MODE(1),
    .C_RX_USER_CLOCKING_CONTENTS(0),
    .C_RX_USER_CLOCKING_INSTANCE_CTRL(0),
    .C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK(1),
    .C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2(1),
    .C_RX_USER_CLOCKING_SOURCE(0),
    .C_RX_USER_DATA_WIDTH(20),
    .C_RX_USRCLK_FREQUENCY(62.5000000),
    .C_RX_USRCLK2_FREQUENCY(62.5000000),
    .C_SECONDARY_QPLL_ENABLE(0),
    .C_SECONDARY_QPLL_REFCLK_FREQUENCY(257.8125),
    .C_TOTAL_NUM_CHANNELS(1),
    .C_TOTAL_NUM_COMMONS(0),
    .C_TOTAL_NUM_COMMONS_EXAMPLE(0),
    .C_TXPROGDIV_FREQ_ENABLE(0),
    .C_TXPROGDIV_FREQ_SOURCE(2),
    .C_TXPROGDIV_FREQ_VAL(62.5),
    .C_TX_BUFFBYPASS_MODE(0),
    .C_TX_BUFFER_BYPASS_INSTANCE_CTRL(0),
    .C_TX_BUFFER_MODE(0),
    .C_TX_DATA_ENCODING(0),
    .C_TX_ENABLE(1),
    .C_TX_INT_DATA_WIDTH(20),
    .C_TX_LINE_RATE(1.25),
    .C_TX_MASTER_CHANNEL_IDX(0),
    .C_TX_OUTCLK_BUFG_GT_DIV(1),
    .C_TX_OUTCLK_FREQUENCY(62.5000000),
    .C_TX_OUTCLK_SOURCE(4),
    .C_TX_PLL_TYPE(2),
    .C_TX_REFCLK_FREQUENCY(100),
    .C_TX_USER_CLOCKING_CONTENTS(0),
    .C_TX_USER_CLOCKING_INSTANCE_CTRL(0),
    .C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK(1),
    .C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2(1),
    .C_TX_USER_CLOCKING_SOURCE(0),
    .C_TX_USER_DATA_WIDTH(20),
    .C_TX_USRCLK_FREQUENCY(62.5000000),
    .C_TX_USRCLK2_FREQUENCY(62.5000000)
    ) inst (
    .gtwiz_userclk_tx_reset_in(gtwiz_userclk_tx_reset_in),
    .gtwiz_userclk_tx_active_in(1'B0),
    .gtwiz_userclk_tx_srcclk_out(gtwiz_userclk_tx_srcclk_out),
    .gtwiz_userclk_tx_usrclk_out(gtwiz_userclk_tx_usrclk_out),
    .gtwiz_userclk_tx_usrclk2_out(gtwiz_userclk_tx_usrclk2_out),
    .gtwiz_userclk_tx_active_out(gtwiz_userclk_tx_active_out),
    .gtwiz_userclk_rx_reset_in(gtwiz_userclk_rx_reset_in),
    .gtwiz_userclk_rx_active_in(1'B0),
    .gtwiz_userclk_rx_srcclk_out(gtwiz_userclk_rx_srcclk_out),
    .gtwiz_userclk_rx_usrclk_out(gtwiz_userclk_rx_usrclk_out),
    .gtwiz_userclk_rx_usrclk2_out(gtwiz_userclk_rx_usrclk2_out),
    .gtwiz_userclk_rx_active_out(gtwiz_userclk_rx_active_out),
    .gtwiz_buffbypass_tx_reset_in(gtwiz_buffbypass_tx_reset_in),
    .gtwiz_buffbypass_tx_start_user_in(gtwiz_buffbypass_tx_start_user_in),
    .gtwiz_buffbypass_tx_done_out(gtwiz_buffbypass_tx_done_out),
    .gtwiz_buffbypass_tx_error_out(gtwiz_buffbypass_tx_error_out),
    .gtwiz_buffbypass_rx_reset_in(gtwiz_buffbypass_rx_reset_in),
    .gtwiz_buffbypass_rx_start_user_in(gtwiz_buffbypass_rx_start_user_in),
    .gtwiz_buffbypass_rx_done_out(gtwiz_buffbypass_rx_done_out),
    .gtwiz_buffbypass_rx_error_out(gtwiz_buffbypass_rx_error_out),
    .gtwiz_reset_clk_freerun_in(gtwiz_reset_clk_freerun_in),
    .gtwiz_reset_all_in(gtwiz_reset_all_in),
    .gtwiz_reset_tx_pll_and_datapath_in(gtwiz_reset_tx_pll_and_datapath_in),
    .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in),
    .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in),
    .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in),
    .gtwiz_reset_tx_done_in(1'B0),
    .gtwiz_reset_rx_done_in(1'B0),
    .gtwiz_reset_qpll0lock_in(1'B0),
    .gtwiz_reset_qpll1lock_in(1'B0),
    .gtwiz_reset_rx_cdr_stable_out(gtwiz_reset_rx_cdr_stable_out),
    .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out),
    .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out),
    .gtwiz_reset_qpll0reset_out(),
    .gtwiz_reset_qpll1reset_out(),
    .gtwiz_gthe3_cpll_cal_txoutclk_period_in(18'B0),
    .gtwiz_gthe3_cpll_cal_cnt_tol_in(18'B0),
    .gtwiz_gthe3_cpll_cal_bufg_ce_in(1'B0),
    .gtwiz_gthe4_cpll_cal_txoutclk_period_in(18'B0),
    .gtwiz_gthe4_cpll_cal_cnt_tol_in(18'B0),
    .gtwiz_gthe4_cpll_cal_bufg_ce_in(1'B0),
    .gtwiz_gtye4_cpll_cal_txoutclk_period_in(18'B0),
    .gtwiz_gtye4_cpll_cal_cnt_tol_in(18'B0),
    .gtwiz_gtye4_cpll_cal_bufg_ce_in(1'B0),
    .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in),
    .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out),
    .bgbypassb_in(1'H1),
    .bgmonitorenb_in(1'H1),
    .bgpdb_in(1'H1),
    .bgrcalovrd_in(5'H1F),
    .bgrcalovrdenb_in(1'H1),
    .drpaddr_common_in(16'H0000),
    .drpclk_common_in(1'H0),
    .drpdi_common_in(16'H0000),
    .drpen_common_in(1'H0),
    .drpwe_common_in(1'H0),
    .gtgrefclk0_in(1'H0),
    .gtgrefclk1_in(1'H0),
    .gtnorthrefclk00_in(1'H0),
    .gtnorthrefclk01_in(1'H0),
    .gtnorthrefclk10_in(1'H0),
    .gtnorthrefclk11_in(1'H0),
    .gtrefclk00_in(1'H0),
    .gtrefclk01_in(1'H0),
    .gtrefclk10_in(1'H0),
    .gtrefclk11_in(1'H0),
    .gtsouthrefclk00_in(1'H0),
    .gtsouthrefclk01_in(1'H0),
    .gtsouthrefclk10_in(1'H0),
    .gtsouthrefclk11_in(1'H0),
    .pcierateqpll0_in(3'H0),
    .pcierateqpll1_in(3'H0),
    .pmarsvd0_in(8'H00),
    .pmarsvd1_in(8'H00),
    .qpll0clkrsvd0_in(1'H0),
    .qpll0clkrsvd1_in(1'H0),
    .qpll0fbdiv_in(8'H00),
    .qpll0lockdetclk_in(1'H0),
    .qpll0locken_in(1'H0),
    .qpll0pd_in(1'H1),
    .qpll0refclksel_in(3'H1),
    .qpll0reset_in(1'H1),
    .qpll1clkrsvd0_in(1'H0),
    .qpll1clkrsvd1_in(1'H0),
    .qpll1fbdiv_in(8'H00),
    .qpll1lockdetclk_in(1'H0),
    .qpll1locken_in(1'H0),
    .qpll1pd_in(1'H1),
    .qpll1refclksel_in(3'H1),
    .qpll1reset_in(1'H1),
    .qpllrsvd1_in(8'H00),
    .qpllrsvd2_in(5'H00),
    .qpllrsvd3_in(5'H00),
    .qpllrsvd4_in(8'H00),
    .rcalenb_in(1'H1),
    .sdm0data_in(25'H0000000),
    .sdm0reset_in(1'H0),
    .sdm0toggle_in(1'H0),
    .sdm0width_in(2'H0),
    .sdm1data_in(25'H0000000),
    .sdm1reset_in(1'H0),
    .sdm1toggle_in(1'H0),
    .sdm1width_in(2'H0),
    .tcongpi_in(10'H000),
    .tconpowerup_in(1'H0),
    .tconreset_in(2'H0),
    .tconrsvdin1_in(2'H0),
    .ubcfgstreamen_in(1'B0),
    .ubdo_in(1'B0),
    .ubdrdy_in(1'B0),
    .ubenable_in(1'B0),
    .ubgpi_in(1'B0),
    .ubintr_in(1'B0),
    .ubiolmbrst_in(1'B0),
    .ubmbrst_in(1'B0),
    .ubmdmcapture_in(1'B0),
    .ubmdmdbgrst_in(1'B0),
    .ubmdmdbgupdate_in(1'B0),
    .ubmdmregen_in(1'B0),
    .ubmdmshift_in(1'B0),
    .ubmdmsysrst_in(1'B0),
    .ubmdmtck_in(1'B0),
    .ubmdmtdi_in(1'B0),
    .drpdo_common_out(),
    .drprdy_common_out(),
    .pmarsvdout0_out(),
    .pmarsvdout1_out(),
    .qpll0fbclklost_out(),
    .qpll0lock_out(),
    .qpll0outclk_out(),
    .qpll0outrefclk_out(),
    .qpll0refclklost_out(),
    .qpll1fbclklost_out(),
    .qpll1lock_out(),
    .qpll1outclk_out(),
    .qpll1outrefclk_out(),
    .qpll1refclklost_out(),
    .qplldmonitor0_out(),
    .qplldmonitor1_out(),
    .refclkoutmonitor0_out(),
    .refclkoutmonitor1_out(),
    .rxrecclk0_sel_out(),
    .rxrecclk1_sel_out(),
    .rxrecclk0sel_out(),
    .rxrecclk1sel_out(),
    .sdm0finalout_out(),
    .sdm0testdata_out(),
    .sdm1finalout_out(),
    .sdm1testdata_out(),
    .tcongpo_out(),
    .tconrsvdout0_out(),
    .ubdaddr_out(),
    .ubden_out(),
    .ubdi_out(),
    .ubdwe_out(),
    .ubmdmtdo_out(),
    .ubrsvdout_out(),
    .ubtxuart_out(),
    .cdrstepdir_in(1'H0),
    .cdrstepsq_in(1'H0),
    .cdrstepsx_in(1'H0),
    .cfgreset_in(1'H0),
    .clkrsvd0_in(1'H0),
    .clkrsvd1_in(1'H0),
    .cpllfreqlock_in(1'H0),
    .cplllockdetclk_in(1'H0),
    .cplllocken_in(1'H1),
    .cpllpd_in(1'H0),
    .cpllrefclksel_in(cpllrefclksel_in),
    .cpllreset_in(1'H0),
    .dmonfiforeset_in(1'H0),
    .dmonitorclk_in(1'H0),
    .drpaddr_in(drpaddr_in),
    .drpclk_in(drpclk_in),
    .drpdi_in(drpdi_in),
    .drpen_in(drpen_in),
    .drprst_in(1'H0),
    .drpwe_in(drpwe_in),
    .elpcaldvorwren_in(1'B0),
    .elpcalpaorwren_in(1'B0),
    .evoddphicaldone_in(1'B0),
    .evoddphicalstart_in(1'B0),
    .evoddphidrden_in(1'B0),
    .evoddphidwren_in(1'B0),
    .evoddphixrden_in(1'B0),
    .evoddphixwren_in(1'B0),
    .eyescanmode_in(1'B0),
    .eyescanreset_in(eyescanreset_in),
    .eyescantrigger_in(1'H0),
    .freqos_in(1'H0),
    .gtgrefclk_in(1'H0),
    .gthrxn_in(gthrxn_in),
    .gthrxp_in(gthrxp_in),
    .gtnorthrefclk0_in(1'H0),
    .gtnorthrefclk1_in(1'H0),
    .gtrefclk0_in(gtrefclk0_in),
    .gtrefclk1_in(1'H0),
    .gtresetsel_in(1'B0),
    .gtrsvd_in(16'H0000),
    .gtrxreset_in(1'H0),
    .gtrxresetsel_in(1'H0),
    .gtsouthrefclk0_in(1'H0),
    .gtsouthrefclk1_in(1'H0),
    .gttxreset_in(1'H0),
    .gttxresetsel_in(1'H0),
    .incpctrl_in(1'H0),
    .gtyrxn_in(1'B0),
    .gtyrxp_in(1'B0),
    .loopback_in(loopback_in),
    .looprsvd_in(1'B0),
    .lpbkrxtxseren_in(1'B0),
    .lpbktxrxseren_in(1'B0),
    .pcieeqrxeqadaptdone_in(1'H0),
    .pcierstidle_in(1'H0),
    .pciersttxsyncstart_in(1'H0),
    .pcieuserratedone_in(1'H0),
    .pcsrsvdin_in(16'H0000),
    .pcsrsvdin2_in(1'B0),
    .pmarsvdin_in(1'B0),
    .qpll0clk_in(1'H0),
    .qpll0freqlock_in(1'H0),
    .qpll0refclk_in(1'H0),
    .qpll1clk_in(1'H0),
    .qpll1freqlock_in(1'H0),
    .qpll1refclk_in(1'H0),
    .resetovrd_in(1'H0),
    .rstclkentx_in(1'B0),
    .rx8b10ben_in(1'H0),
    .rxafecfoken_in(1'H1),
    .rxbufreset_in(1'H0),
    .rxcdrfreqreset_in(1'H0),
    .rxcdrhold_in(1'H0),
    .rxcdrovrden_in(1'H0),
    .rxcdrreset_in(1'H0),
    .rxcdrresetrsv_in(1'B0),
    .rxchbonden_in(1'H0),
    .rxchbondi_in(5'H00),
    .rxchbondlevel_in(3'H0),
    .rxchbondmaster_in(1'H0),
    .rxchbondslave_in(1'H0),
    .rxckcalreset_in(1'H0),
    .rxckcalstart_in(7'H00),
    .rxcommadeten_in(1'H1),
    .rxdfeagcctrl_in(2'H1),
    .rxdccforcestart_in(1'B0),
    .rxdfeagchold_in(1'H0),
    .rxdfeagcovrden_in(1'H0),
    .rxdfecfokfcnum_in(4'HD),
    .rxdfecfokfen_in(1'H0),
    .rxdfecfokfpulse_in(1'H0),
    .rxdfecfokhold_in(1'H0),
    .rxdfecfokovren_in(1'H0),
    .rxdfekhhold_in(1'H0),
    .rxdfekhovrden_in(1'H0),
    .rxdfelfhold_in(1'H0),
    .rxdfelfovrden_in(1'H0),
    .rxdfelpmreset_in(1'H0),
    .rxdfetap10hold_in(1'H0),
    .rxdfetap10ovrden_in(1'H0),
    .rxdfetap11hold_in(1'H0),
    .rxdfetap11ovrden_in(1'H0),
    .rxdfetap12hold_in(1'H0),
    .rxdfetap12ovrden_in(1'H0),
    .rxdfetap13hold_in(1'H0),
    .rxdfetap13ovrden_in(1'H0),
    .rxdfetap14hold_in(1'H0),
    .rxdfetap14ovrden_in(1'H0),
    .rxdfetap15hold_in(1'H0),
    .rxdfetap15ovrden_in(1'H0),
    .rxdfetap2hold_in(1'H0),
    .rxdfetap2ovrden_in(1'H0),
    .rxdfetap3hold_in(1'H0),
    .rxdfetap3ovrden_in(1'H0),
    .rxdfetap4hold_in(1'H0),
    .rxdfetap4ovrden_in(1'H0),
    .rxdfetap5hold_in(1'H0),
    .rxdfetap5ovrden_in(1'H0),
    .rxdfetap6hold_in(1'H0),
    .rxdfetap6ovrden_in(1'H0),
    .rxdfetap7hold_in(1'H0),
    .rxdfetap7ovrden_in(1'H0),
    .rxdfetap8hold_in(1'H0),
    .rxdfetap8ovrden_in(1'H0),
    .rxdfetap9hold_in(1'H0),
    .rxdfetap9ovrden_in(1'H0),
    .rxdfeuthold_in(1'H0),
    .rxdfeutovrden_in(1'H0),
    .rxdfevphold_in(1'H0),
    .rxdfevpovrden_in(1'H0),
    .rxdfevsen_in(1'B0),
    .rxdfexyden_in(1'H1),
    .rxdlybypass_in(1'H0),
    .rxdlyen_in(1'H0),
    .rxdlyovrden_in(1'H0),
    .rxdlysreset_in(1'H0),
    .rxelecidlemode_in(2'H3),
    .rxeqtraining_in(1'H0),
    .rxgearboxslip_in(1'H0),
    .rxlatclk_in(1'H0),
    .rxlpmen_in(rxlpmen_in),
    .rxlpmgchold_in(1'H0),
    .rxlpmgcovrden_in(1'H0),
    .rxlpmhfhold_in(1'H0),
    .rxlpmhfovrden_in(1'H0),
    .rxlpmlfhold_in(1'H0),
    .rxlpmlfklovrden_in(1'H0),
    .rxlpmoshold_in(1'H0),
    .rxlpmosovrden_in(1'H0),
    .rxmcommaalignen_in(1'H0),
    .rxmonitorsel_in(2'H0),
    .rxoobreset_in(1'H0),
    .rxoscalreset_in(1'H0),
    .rxoshold_in(1'H0),
    .rxosintcfg_in(1'B0),
    .rxosinten_in(1'B0),
    .rxosinthold_in(1'B0),
    .rxosintovrden_in(1'B0),
    .rxosintstrobe_in(1'B0),
    .rxosinttestovrden_in(1'B0),
    .rxosovrden_in(1'H0),
    .rxoutclksel_in(3'H2),
    .rxpcommaalignen_in(1'H0),
    .rxpcsreset_in(1'H0),
    .rxpd_in(2'H0),
    .rxphalign_in(1'H0),
    .rxphalignen_in(1'H0),
    .rxphdlypd_in(1'H0),
    .rxphdlyreset_in(1'H0),
    .rxphovrden_in(1'H0),
    .rxpllclksel_in(2'H0),
    .rxpmareset_in(1'H0),
    .rxpolarity_in(1'H0),
    .rxprbscntreset_in(1'H0),
    .rxprbssel_in(4'H0),
    .rxprogdivreset_in(1'H0),
    .rxqpien_in(1'H0),
    .rxrate_in(rxrate_in),
    .rxratemode_in(1'H0),
    .rxslide_in(rxslide_in),
    .rxslipoutclk_in(1'H0),
    .rxslippma_in(1'H0),
    .rxsyncallin_in(1'H0),
    .rxsyncin_in(1'H0),
    .rxsyncmode_in(1'H0),
    .rxsysclksel_in(2'H0),
    .rxtermination_in(1'H0),
    .rxuserrdy_in(1'H1),
    .rxusrclk_in(1'H0),
    .rxusrclk2_in(1'H0),
    .sigvalidclk_in(1'H0),
    .tstin_in(20'H00000),
    .tx8b10bbypass_in(8'H00),
    .tx8b10ben_in(1'H0),
    .txbufdiffctrl_in(1'B0),
    .txcominit_in(1'H0),
    .txcomsas_in(1'H0),
    .txcomwake_in(1'H0),
    .txctrl0_in(16'H0000),
    .txctrl1_in(16'H0000),
    .txctrl2_in(8'H00),
    .txdata_in(128'H00000000000000000000000000000000),
    .txdataextendrsvd_in(8'H00),
    .txdccforcestart_in(1'H0),
    .txdccreset_in(1'H0),
    .txdeemph_in(2'H0),
    .txdetectrx_in(1'H0),
    .txdiffctrl_in(txdiffctrl_in),
    .txdiffpd_in(1'B0),
    .txdlybypass_in(1'H0),
    .txdlyen_in(1'H0),
    .txdlyhold_in(1'H0),
    .txdlyovrden_in(1'H0),
    .txdlysreset_in(1'H0),
    .txdlyupdown_in(1'H0),
    .txelecidle_in(1'H0),
    .txelforcestart_in(1'B0),
    .txheader_in(6'H00),
    .txinhibit_in(1'H0),
    .txlatclk_in(1'H0),
    .txlfpstreset_in(1'H0),
    .txlfpsu2lpexit_in(1'H0),
    .txlfpsu3wake_in(1'H0),
    .txmaincursor_in(7'H00),
    .txmargin_in(3'H0),
    .txmuxdcdexhold_in(1'H0),
    .txmuxdcdorwren_in(1'H0),
    .txoneszeros_in(1'H0),
    .txoutclksel_in(3'H5),
    .txpcsreset_in(1'H0),
    .txpd_in(2'H0),
    .txpdelecidlemode_in(1'H0),
    .txphalign_in(1'H0),
    .txphalignen_in(1'H0),
    .txphdlypd_in(1'H0),
    .txphdlyreset_in(1'H0),
    .txphdlytstclk_in(1'H0),
    .txphinit_in(1'H0),
    .txphovrden_in(1'H0),
    .txpippmen_in(1'H0),
    .txpippmovrden_in(1'H0),
    .txpippmpd_in(1'H1),
    .txpippmsel_in(1'H0),
    .txpippmstepsize_in(5'H00),
    .txpisopd_in(1'H0),
    .txpllclksel_in(2'H0),
    .txpmareset_in(1'H0),
    .txpolarity_in(1'H0),
    .txpostcursor_in(txpostcursor_in),
    .txpostcursorinv_in(1'B0),
    .txprbsforceerr_in(1'H0),
    .txprbssel_in(4'H0),
    .txprecursor_in(txprecursor_in),
    .txprecursorinv_in(1'B0),
    .txprogdivreset_in(1'H0),
    .txqpibiasen_in(1'H0),
    .txqpistrongpdown_in(1'B0),
    .txqpiweakpup_in(1'H0),
    .txrate_in(3'H0),
    .txratemode_in(1'H0),
    .txsequence_in(7'H00),
    .txswing_in(1'H0),
    .txsyncallin_in(1'H0),
    .txsyncin_in(1'H0),
    .txsyncmode_in(1'H0),
    .txsysclksel_in(2'H0),
    .txuserrdy_in(1'H1),
    .txusrclk_in(1'H0),
    .txusrclk2_in(1'H0),
    .bufgtce_out(),
    .bufgtcemask_out(),
    .bufgtdiv_out(),
    .bufgtreset_out(),
    .bufgtrstmask_out(),
    .cpllfbclklost_out(),
    .cplllock_out(),
    .cpllrefclklost_out(),
    .dmonitorout_out(),
    .dmonitoroutclk_out(),
    .drpdo_out(drpdo_out),
    .drprdy_out(drprdy_out),
    .eyescandataerror_out(),
    .gthtxn_out(gthtxn_out),
    .gthtxp_out(gthtxp_out),
    .gtpowergood_out(gtpowergood_out),
    .gtrefclkmonitor_out(),
    .gtytxn_out(),
    .gtytxp_out(),
    .pcierategen3_out(),
    .pcierateidle_out(),
    .pcierateqpllpd_out(),
    .pcierateqpllreset_out(),
    .pciesynctxsyncdone_out(),
    .pcieusergen3rdy_out(),
    .pcieuserphystatusrst_out(),
    .pcieuserratestart_out(),
    .pcsrsvdout_out(),
    .phystatus_out(),
    .pinrsrvdas_out(),
    .powerpresent_out(),
    .resetexception_out(),
    .rxbufstatus_out(),
    .rxbyteisaligned_out(),
    .rxbyterealign_out(),
    .rxcdrlock_out(),
    .rxcdrphdone_out(),
    .rxchanbondseq_out(),
    .rxchanisaligned_out(),
    .rxchanrealign_out(),
    .rxchbondo_out(),
    .rxckcaldone_out(),
    .rxclkcorcnt_out(),
    .rxcominitdet_out(),
    .rxcommadet_out(),
    .rxcomsasdet_out(),
    .rxcomwakedet_out(),
    .rxctrl0_out(),
    .rxctrl1_out(),
    .rxctrl2_out(),
    .rxctrl3_out(),
    .rxdata_out(),
    .rxdataextendrsvd_out(),
    .rxdatavalid_out(),
    .rxdlysresetdone_out(),
    .rxelecidle_out(),
    .rxheader_out(),
    .rxheadervalid_out(),
    .rxlfpstresetdet_out(),
    .rxlfpsu2lpexitdet_out(),
    .rxlfpsu3wakedet_out(),
    .rxmonitorout_out(),
    .rxosintdone_out(),
    .rxosintstarted_out(),
    .rxosintstrobedone_out(),
    .rxosintstrobestarted_out(),
    .rxoutclk_out(),
    .rxoutclkfabric_out(),
    .rxoutclkpcs_out(),
    .rxphaligndone_out(),
    .rxphalignerr_out(),
    .rxpmaresetdone_out(rxpmaresetdone_out),
    .rxprbserr_out(),
    .rxprbslocked_out(),
    .rxprgdivresetdone_out(),
    .rxqpisenn_out(),
    .rxqpisenp_out(),
    .rxratedone_out(),
    .rxrecclkout_out(),
    .rxresetdone_out(rxresetdone_out),
    .rxsliderdy_out(),
    .rxslipdone_out(),
    .rxslipoutclkrdy_out(),
    .rxslippmardy_out(),
    .rxstartofseq_out(),
    .rxstatus_out(),
    .rxsyncdone_out(),
    .rxsyncout_out(),
    .rxvalid_out(),
    .txbufstatus_out(),
    .txcomfinish_out(),
    .txdccdone_out(),
    .txdlysresetdone_out(),
    .txoutclk_out(),
    .txoutclkfabric_out(),
    .txoutclkpcs_out(),
    .txphaligndone_out(),
    .txphinitdone_out(),
    .txpmaresetdone_out(txpmaresetdone_out),
    .txprgdivresetdone_out(txprgdivresetdone_out),
    .txqpisenn_out(),
    .txqpisenp_out(),
    .txratedone_out(),
    .txresetdone_out(txresetdone_out),
    .txsyncdone_out(),
    .txsyncout_out()
    );
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_gthe4_channel_wrapper.v 0 → 100644
    View file @ d7c7b52e
    This source diff could not be displayed because it is too large. You can view the blob instead.
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_ooc.xdc 0 → 100644
    View file @ d7c7b52e
    #------------------------------------------------------------------------------
    # (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
    #
    # This file contains confidential and proprietary information
    # of Xilinx, Inc. and is protected under U.S. and
    # international copyright and other intellectual property
    # laws.
    #
    # DISCLAIMER
    # This disclaimer is not a license and does not grant any
    # rights to the materials distributed herewith. Except as
    # otherwise provided in a valid license issued to you by
    # Xilinx, and to the maximum extent permitted by applicable
    # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    # (2) Xilinx shall not be liable (whether in contract or tort,
    # including negligence, or under any other theory of
    # liability) for any loss or damage of any kind or nature
    # related to, arising under or in connection with these
    # materials, including for any direct, or any indirect,
    # special, incidental, or consequential loss or damage
    # (including loss of data, profits, goodwill, or any type of
    # loss or damage suffered as a result of any action brought
    # by a third party) even if such damage or loss was
    # reasonably foreseeable or Xilinx had been advised of the
    # possibility of the same.
    #
    # CRITICAL APPLICATIONS
    # Xilinx products are not designed or intended to be fail-
    # safe, or for use in any application requiring fail-safe
    # performance, such as life-support or safety devices or
    # systems, Class III medical devices, nuclear facilities,
    # applications related to the deployment of airbags, or any
    # other applications that could lead to death, personal
    # injury, or severe property or environmental damage
    # (individually and collectively, "Critical
    # Applications"). Customer assumes the sole risk and
    # liability of any use of Xilinx products in Critical
    # Applications, subject only to applicable laws and
    # regulations governing limitations on product liability.
    #
    # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    # PART OF THIS FILE AT ALL TIMES.
    #------------------------------------------------------------------------------
    # UltraScale FPGAs Transceivers Wizard IP core-level XDC file for out-of-context flows
    # ----------------------------------------------------------------------------------------------------------------------
    # This constraints file contains default clock frequencies to be used during out-of-context flows such as
    # OOC Synthesis and Hierarchical Designs.
    # Free-running clock constraint
    create_clock -period 16.0 [get_ports gtwiz_reset_clk_freerun_in]
    # CPLL reference clock constraint (will be overridden by required constraint on IBUFDS_GTE4 input in context)
    create_clock -period 10.0 [get_ports gtrefclk0_in[0]]
    # DRP clock constraint for CHANNEL primitive
    create_clock -period 16.0 [get_ports drpclk_in[0]]
    ##set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}] -quiet
    set_false_path -to [get_pins -filter {REF_PIN_NAME=~*D} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta*}]] -quiet
    set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta*}]] -quiet
    set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync1*}]] -quiet
    set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync2*}]] -quiet
    set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync3*}]] -quiet
    set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_out*}]] -quiet
    set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta*}]] -quiet
    set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync1*}]] -quiet
    set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync2*}]] -quiet
    set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync3*}]] -quiet
    set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_out*}]] -quiet
    # False path constraints
    # ----------------------------------------------------------------------------------------------------------------------
    set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_tx_inst/*gtwiz_userclk_tx_active_*_reg}] -quiet
    set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_rx_inst/*gtwiz_userclk_rx_active_*_reg}] -quiet
    platform/xilinx/wr_xilinx_pkg.vhd
    View file @ d7c7b52e
    ......@@ -35,6 +35,7 @@ use ieee.std_logic_1164.all;
    library work;
    use work.endpoint_pkg.all;
    use work.wishbone_pkg.all;
    package wr_xilinx_pkg is
    ......@@ -238,12 +239,13 @@ package wr_xilinx_pkg is
    component wr_gtx_phy_family7_lp is
    generic (
    -- set to non-zero value to speed up the simulation by reducing some delays
    g_simulation : integer := 0;
    g_id : integer := 0);
    g_simulation : integer := 0);
    port (
    clk_gtx_i : in std_logic;
    clk_dmtd_i : in std_logic;
    clk_ref_i : in std_logic;
    clk_sys_i : in std_logic;
    rst_sys_n_i : in std_logic;
    tx_out_clk_o : out std_logic;
    tx_locked_o : out std_logic;
    tx_data_i : in std_logic_vector(15 downto 0);
    ......@@ -264,8 +266,8 @@ package wr_xilinx_pkg is
    pad_rxn_i : in std_logic := '0';
    pad_rxp_i : in std_logic := '0';
    rdy_o : out std_logic;
    lpc_ctrl_i : in std_logic_vector(15 downto 0) := x"0000";
    lpc_stat_o : out std_logic_vector(15 downto 0);
    mdio_slave_i : in t_wishbone_slave_in;
    mdio_slave_o : out t_wishbone_slave_out;
    fmon_clk_tx_o : out std_logic;
    fmon_clk_tx2_o : out std_logic;
    fmon_clk_rx_o : out std_logic);
    ......@@ -335,6 +337,8 @@ package wr_xilinx_pkg is
    port (
    clk_gth_i : in std_logic;
    clk_dmtd_i : in std_logic;
    clk_sys_i : in std_logic;
    rst_sys_n_i : in std_logic;
    tx_out_clk_o : out std_logic;
    tx_locked_o : out std_logic;
    tx_data_i : in std_logic_vector(15 downto 0);
    ......@@ -350,13 +354,13 @@ package wr_xilinx_pkg is
    rst_i : in std_logic;
    loopen_i : in std_logic;
    tx_prbs_sel_i : in std_logic_vector(2 downto 0);
    lpc_ctrl_i : in std_logic_vector(15 downto 0) := x"0000";
    lpc_stat_o : out std_logic_vector(15 downto 0);
    pad_txn_o : out std_logic;
    pad_txp_o : out std_logic;
    pad_rxn_i : in std_logic := '0';
    pad_rxp_i : in std_logic := '0';
    rdy_o : out std_logic
    rdy_o : out std_logic;
    mdio_slave_i : in t_wishbone_slave_in;
    mdio_slave_o : out t_wishbone_slave_out
    );
    end component;
    ......
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