Add reference design for Xilinx Zynq
Release v4.2 contains a new reference design for a Xilinx Zynq-based
board FASEC
The new reference design consists of a FASEC Board Support Package,
built as Vivado IP Core and a reference top design assembled with Zynq
processing system as a Vivado block diagram. The whole design can be
re-generated using TCL scripts as described in the release user manual.