Open Hardware Repository

The nanoFIP test board is used to test the functionality of the nanoFIP design. Apart from the nanoFIP chip, the FielDrive and the FieldTR it houses another Actel FPGA that can access nanoFIP in stand-alone or in memory mode. This FPGA can also communicate through a RS232 port with a windows PC running the NFTC software....

A Trigger/Timing Logic Unit designed for use with High Energy Physics beam-tests. Provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope. Implemented as a double-width FMC....

General application FMC card that can be used to acquire signals from a variety of sensors - thermopiles, RTDs, resistive bridges......

A simple card that measures temperatures using low cost external Silicon sensors (just ordinary bipolar transistors). On the front panel it has 8 mini-jack connectors to quickly rearrange the setup....

An FMC board with an analog 125 MS/s input and an analog 600 MS/s output for RF applications....

The FmcAdc1G12b2cha is a 2 channel 1GSPS 10 bit ADC card in FMC (FPGA Mezzanine Card) format using an LPC connector. The gain can be set by software in three steps: +/-50mV, +/-0.5V, +/-5V. An offset circuit is used in the front-end design of the ADC board and allows a voltage shift in the same range as the chosen gain....

The FmcAdc250M12b2cha is a 2 channel 250MSPS 12 bit ADC card in FMC (FPGA Mezzanine Card) format using an LPC connector. The gain can be set by software in three steps: +/-50mV, +/-0.5V, +/-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of +/- 5V that is independent on the chosen gain range....

FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os that are on LEMO 00 connectors are TTL compatible....

FmcAdc200k16b11cha is an 11 channel 200kSPS 16 bit ADC card in FMC (FPGA Mezzanine Card) standard. The input voltage range is settable to +/-10V or +/-5V. The input impedance is 1MOhm....

FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC card in FMC (FPGA Mezzanine Card) standard with LPC connector. Gain can be programmed in three steps: +/-50mV, +/-0.5V, +/-5V. The offset correction is added in front of the ADC board and a voltage shift in the range of +/- 5V is possible for each gain range. ...

A four channel 125MSPS/16b analog to digital converter, with a 40MHz input bandwidth, +13dBm max. input power and 80dBFS dynamic range. FMC module in low stacking height (8.5mm) and high pin count connector. Channels are concentrated in pairs, with independent clocks per pair and LVDS DDR output option for full speed sampling....

An FMC to test the correct mounting of FMC connectors on FMC carrier boards....

FMC DAC 10M 16b 4cha: 16-bit 10Ms/s DAC card in FMC form-factor. Four channels with an output range of +/-10V. Three trigger inputs (start, pause and stop), common to the four outputs....

An HPC FMC with 4 Digital to Analog Converter channels working at 250 MS/s with 16-bit resolution....

A two channel DDS based low jitter clock generator....

A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns....

FmcDIO16chTTLa is a 2x 8-bit port digital IO card in FMC form-factor. Each 8-bit port can be configured individually as input or output. IOs are TTL compatible. Additional test features can be mounted on the PCB....

An LPC FMC board which seeks to distribute digital I/O. It is designed to operate at least at 10 MHz, however a better design could allow this board to operate at much higher frequencies. This board is compatible with "PMOD" Connectors. ...

The PFC is a 4-lane PCIe carrier for a single VITA 57 (FMC) mezzanine. It has many memory and clocking resources and supports the White Rabbit timing and control network....

FMC carrier equipped with a Power PC embedded processor. In addition to the SPEC it has 2 gigabit Ethernet ports, one mini PCIe connector and USB 2.0 HS. It is supplied from a single 12V and runs Linux. The FPGA is configured from the processor and also interfaced using PCI Express x1 and a local bus. The system boots from on-board NAND or NOR flash memory....

An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements....

The project is about building an FPGA Mezzanine card (standard FMC/Vita 57) for high-channel-count electrophysiology, on the order of 128 channels (up to 512), based upon Intan Tech's RHA2132 (2 uV rms input-referred noise), sampled at above 25kHz 18bit. It should be a simple project on the digital side but the low-noise amplifiers are finicky and the connectors to the electrophysiology rig might be tricky. We might be able to get away with a USB carrier card at the bandwidths we intend. ...

A Virtex6-based optical link interface AMC equipped with SFP+ and FMC sockets...

RHINO (Reconfigurable Hardware Interface for Computing and Radio) is a compute platform consisting of a single FPGA element with memory, high speed communication, and FMC-LPC (Vita 57.1) IO expansion slots, all controlled via an ARM Cortex A8 processor running the BORPH operating system. For up to data progress, follow us on twitter @rhinoplatform....

A simple 4-lane PCIe carrier for FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network....

A simple 4-lane PXIe carrier for FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network....

A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network....

An FMC for clock & data recovery from optical sources....

The VFC is a VME carrier for two VITA 57 (FMC) mezzanines. ...

A High Pin Count FMC carrier in VXS format with two Virtex 5 FPGAs plus a DSP on board....

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen....

Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet. ...

This project defines an area of common registers inside FPGAs, which allows for unambiguous identification of the FPGA bitstream and automatic probing of internal Wishbone cores by external software....

A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone. ...

IPBus is a FPGA Core that controls a Wishbone bus via Ethernet. Currently the transport protocol is UDP/IP, although there are plans for an ATA over Ethernet (AoE) implementation. There are reference designs for the SP601 and SP605 Xilinx FPGA boards....

The LatticeMico32 processor is a Verilog core for a 5-stage pipelined RISC architecture. Originally designed for Lattice FPGAs, this project modifies it to support Altera and Xilinx. It has GNU toolchain support since gcc 4.5. This code is a fork of the milkymist fork of the original LM32 design....

A collection of platform-independent cores such as memories and synchronizer circuits....

A QDR II RAM controller for the Virtex 6 FPGA family. This core is compliant with the Wishbone bus....

A Time to Digital Converter core for Spartan 6 FPGAs....

A VHDL core for a VME64x slave (Wishbone master)....

A collection of cores needed in the White Rabbit node and switch....

A White Rabbit node core containing the WR PTP core, Etherbone, an embedded CPU, etc....

A Wishbone B.4 crossbar in VHDL. Also includes some records to simplify Wishbone interface inputs/outputs....

A project to establish a transparent Wishbone bridge between two FPGAs using high-speed serial links....

wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:...

A level conversion board in VME64x form factor between TTL and Blocking Levels. Direction and levels are configurable. The project uses a Rear Transition Module for connectivity and a Front module with the active conversion and diagnostics electronics....

A three-channel TTL to NIM (Nuclear Instrumentation Module) level conversion board in VME form factor....

A level conversion board in VME64x double-height form factor between TTL and RS485. Direction and levels are configurable. The project uses a Rear Transition Module for connectivity and a Front module with the active conversion and diagnostics electronics....

ADC testing procedures and software....

A project to describe techniques and gather results of the time transfer between CERN and LNGS for the neutrino Time Of Flight experiment....

GTS is a tool which takes a binary for a given microprocessor (initially an LM32) and gives information about worst-case execution time....

Tool for generating multi-purpose makefiles for FPGA projects. ...

PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor....

A software suite written in Python to help with production tests of PCBs....

A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware....

Firmware for ROBIN-NP project....

Hardware designs for ROBIN-NP project....

Software for ROBIN-NP project....

A Precise Time Protocol (PTP, IEEE 1588) software stack whose single source code can be compiled for many architectures (POSIX systems, SPEC...) and which is easily extensible....

A White Rabbit compliant Network Interface Card (NIC) based on the SPEC and the DIO FMC. This project hosts the HDL and associated software to configure the SPEC so it behaves as a NIC under the Linux OS....

The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered. ...

This project contains all the HDL necessary for the FPGA of the WR switch....

Development of software for the White Rabbit switch, and in particular the embedded Linux system running in the ARM9 processor....

A project to host all software and hardware developments related to testing the White Rabbit switch....