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  • ARMadillo
    A multi-purpose ARM-based small piggy-back PCB with Linux support, Ethernet, USB, sound, graphic LCD and lots of I/O pins....
  • Beam Position Monitor
    Sub-micrometer resolution beam position monitoring system (BPM) for accelerators. It provides real-time orbit monitoring, buffered data readouts, fast orbit feedback capabilities and advanced beam diagnostics tools....
    • BPM Digital Back-End
      Hardware platform for implementation of digital signal processing for BPM data paths, data acquisition, orbit feedback control algorithms and accelerator’s control system interface....
    • BPM RF Front-End
      Signal conditioning electronics for BPM pick-ups providing 4-channel RF signal analog filtering, amplification, digitally controlled attenuation and several calibration schemes....
    • BPM Firmware and Software
      Software and FPGA firmware for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface....
  • CERN ELMB
    ELMB is an analog/digital input/output module with CANbus interface. About 10000 of ELMBs are used in various CERN installations of experiments running on LHC, mostly for monitoring and control of experiments. It is proved not to break after intercepting big doses of radiation....
  • CERN Open Hardware Licence
    • Status: Release
    A project devoted to developing and discussing the CERN Open Hardware Licence....
  • CernFIP
    • Status: Release
    WorldFIP is a deterministic rad-tol fieldbus used at CERN's LHC for a variety of control systems....
    • nanoFIPDiag
      nanoFIPDiag is a WorldFIP module dedicated to monitoring and diagnostics. It uses a NanoFIP chip in order to be Radiation Tolerant....
    • nanoFIP Test Board
      • Status: Beta
      The nanoFIP test board is used to test the functionality of the nanoFIP design. Apart from the nanoFIP chip, the FielDrive and the FieldTR it houses another Actel FPGA that can access nanoFIP in stand-alone or in memory mode. This FPGA can also communicate through a RS232 port with a windows PC running the NFTC software....
  • FIP Converter
    A converter between USB/Ethernet and WorldFIP, allowing the bus arbitration and control of a WorldFIP fieldbus segment from a USB or Ethernet-equipped computer....
  • FMC Projects
    FMCprojects shows the FMC Mezzanine and Carrier boards that are developed in the Open Hardware Repository context. Furthermore it gives useful data helping you to design modules complying to this VITA 57.1 standard. This actually is not a hardware project, but is there to help you find your way in the FMC standard and shows you which FMC Mezzanines and Carriers are being developed in the context of the Open Hardware project. ...
    • AMC FMC Carrier (AFC)
      AMC FMC Carrier.More info at the Wiki page...
    • AIDA mini-TLU
      A Trigger/Timing Logic Unit designed for use with High Energy Physics beam-tests. Provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope. Implemented as a double-width FMC....
    • FMC 8 channel slow signal conditioner with 24 bit sigma delta ADC
      General application FMC card that can be used to acquire signals from a variety of sensors - thermopiles, RTDs, resistive bridges......
    • FMC 8 channel temperature monitor
      A simple card that measures temperatures using low cost external Silicon sensors (just ordinary bipolar transistors). On the front panel it has 8 mini-jack connectors to quickly rearrange the setup....
    • FMC ADC 100M 14b 4cha
      FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). Input ranges: +/-50mV, +/-0.5V, +/-5V. The offset correction by +/- 5V is possible for each gain range. Commercially available....
    • FMC ADC 10M 16b 2ch DAC 50M 16b 2ch
      The Peak Position Detector is a 2 differential channel 10MSPS 16 bit ADC (AD7626) card in FMC (FPGA Mezzanine Card) format. It uses an LPC VITA57 connector. The gain can be set by hardware (default = 41). Two general purpose 50MSPS 16-Bit DAC are implemented and can be programmed as a voltage source....
    • FMC ADC 125M 14b 1ch DAC 600M 14b 1ch
      An FMC board with an analog 125 MS/s input and an analog 600 MS/s output for RF applications....
      • Software support for FMC ADC 125M 14B 1CH DAC 600M 14B 1CH
        Software to support the FMC ADC 125M 14B 1CH DAC 600M 14B 1CH mezzanine, including: Linux device driver, HDL firmware, application for data acquisition (ADC) and generating signals (DAC). Included Octave application for card performance measurement (FFT). Uses FMC-bus....
    • FMC ADC 130M 16b 4cha
      4-channel 16-bit 130 MS/s (700 MHz analog input bandwidth) ADC (LTC2208) FMC module....
      • Software support for FMC ADC 130M 16B 4CH
        Software to support the FMC ADC 130M 16B 4CH mezzanine, including: configuration application and HDL firmware, with functionality for data acqusition. For use with FCS application....
    • FMC ADC 1G 10b 2cha
      The FmcAdc1G12b2cha is a 2 channel 1GSPS 10 bit ADC card in FMC (FPGA Mezzanine Card) format using an LPC connector. The gain can be set by software in three steps: +/-50mV, +/-0.5V, +/-5V. An offset circuit is used in the front-end design of the ADC board and allows a voltage shift in the same range as the chosen gain....
    • FMC ADC 200k 16b 11cha
      FmcAdc200k16b11cha is an 11 channel 200kSPS 16 bit ADC card in FMC (FPGA Mezzanine Card) standard. The input voltage range is settable to +/-10V or +/-5V. The input impedance is 1MOhm....
    • FMC ADC 250M 12b 2cha
      The FmcAdc250M12b2cha is a 2 channel 250MSPS 12 bit ADC card in FMC (FPGA Mezzanine Card) format using an LPC connector. The gain can be set by software in three steps: +/-50mV, +/-0.5V, +/-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of +/- 5V that is independent on the chosen gain range....
    • FMC ADC 250M 16b 4cha
      4-channel 16-bit 250 MS/s (700 MHz analog input bandwidth) ADC (ISLA216P25) FMC module....
      • Software support for FMC ADC 250M 16B 4CH
        Software to support the FMC ADC 250M 16B 4CH mezzanine, including: configuration application and HDL firmware, with functionality for data acqusition. For use with FCS application....
    • FMC ADC 2M 18b 2ch DAC 500k 20b 1ch
      The B-Train integrator is a 2 differential channel 2MSPS 18 bit ADC card in FMC (FPGA Mezzanine Card) format. It uses an LPC VITA57 connector. The gain can be set by hardware (default = 1). A gain & offset self-calibrating function is also implemented. This function uses a 1ppm 20-Bit DAC (AD5791) as a reference and can be programmed as a differential voltage source. The card also includes 8 input/output LVDS pairs and a 10-bit port digital IO where each single-bit port can be configured individually as input or output. The I/Os that are on micro-HDMI connectors are TTL or LVDS compatible....
    • FMC Carrier tester
      An FMC to test the correct mounting of FMC connectors on FMC carrier boards....
    • FMC DAC 10M 16b 4cha
      • Status: Planning
      FMC DAC 10M 16b 4cha: 16-bit 10Ms/s DAC card in FMC form-factor. Four channels with an output range of +/-10V. Three trigger inputs (start, pause and stop), common to the four outputs....
    • FMC DAC 130M 12b 4ch 4SFP
      FMC with 4 SFPs, 4 DACs, and 4 TLK2501 chips. The board receives data streams from remote ADCs using an optical serial interface and produces analog outputs for monitoring purposes....
    • FMC DAC 250M 16b 4cha
      • Status: Beta
      An HPC FMC with 4 Digital to Analog Converter channels working at 250 MS/s with 16-bit resolution....
    • FMC DAC 600M 12b 1cha DDS
      An FMC for Direct Digital Synthesis (DDS) applications. It contains a DAC, a phase detector and a PLL chip....
    • FMC DEL 1ns 4cha
      A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns. Commercially available....
    • FMC DIO 16ch TTL a
      FmcDIO16chTTLa is a 2x 8-bit port digital IO card in FMC form-factor. Each 8-bit port can be configured individually as input or output. IOs are TTL compatible. Additional test features can be mounted on the PCB....
    • FMC DIO 32ch TTL a
      FmcDIO32chTTLa is a 32-bit port digital IO card in FMC form-factor. ...
      • Software support for FMC DIO 32CH TTL A
        Software to support the FMC DIO 32CH TTL A mezzanine, including: configuration application and HDL firmware, with functionality for data acqusition. For use with FCS application....
    • FMC DIO 5ch TTL a
      FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os that are on LEMO 00 connectors are TTL compatible....
    • FMC LPC 100 Mil 12 Pin Digital I/O Expansion Board
      An LPC FMC board which seeks to distribute digital I/O. It is designed to operate at least at 10 MHz, however a better design could allow this board to operate at much higher frequencies. This board is compatible with "PMOD" Connectors. ...
    • FMC PCIe Carrier (PFC)
      • Status: Alpha
      The PFC is a 4-lane PCIe carrier for a single VITA 57 (FMC) mezzanine. It has many memory and clocking resources and supports the White Rabbit timing and control network....
    • FMC PowerPC carrier (SPEC-based)
      FMC carrier equipped with a Power PC embedded processor. In addition to the SPEC it has 2 gigabit Ethernet ports, one mini PCIe connector and USB 2.0 HS. It is supplied from a single 12V and runs Linux. The FPGA is configured from the processor and also interfaced using PCI Express x1 and a local bus. The system boots from on-board NAND or NOR flash memory....
    • FMC TDC 1ns 5cha
      An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available....
      • FMC TDC SW support
        Host-side software support for the TDC FMC on the SPEC and SVEC FMC carriers....
    • HiCCE-FMC-128
      We are designing an FPGA Mezzanine card (standard FMC/Vita 57) for high-channel-count electrophysiology, with 128 channels (potentially up to 512), based upon Intan Tech's RHA2132 (2 uV rms input-referred noise), sampled at 25kHz 18bit by AD7982. We are basing our design on the reference design provided by Reid Harrison of Intan Tech for their 16-channel evaluation board. ...
    • Optical Clock & Data Recovery FMC
      An FMC for clock & data recovery from optical sources....
    • Optical link interface AMC
      A Virtex6-based optical link interface AMC equipped with SFP+ and FMC sockets...
    • RHINO
      RHINO (Reconfigurable Hardware Interface for Computing and Radio) is a compute platform consisting of a single FPGA element with memory, high speed communication, and FMC-LPC (Vita 57.1) IO expansion slots, all controlled via an ARM Cortex A8 processor running the BORPH operating system. For up to data progress, follow us on twitter @rhinoplatform....
    • Simple PCIe FMC carrier (SPEC)
      A simple 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available....
    • Simple PXIe FMC Carrier (SPEXI)
      A simple 4-lane PXIe carrier for FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Design based on the SPEC....
    • Simple VME FMC Carrier (SVEC)
      A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available....
    • Stand-alone 18-slot FMC carrier
      Stand Alone Carrier with 18 FMC LPC slots based on Spartan FPGAs, mini-ITX board and ATX supply....
    • VME FMC Carrier (VFC)
      • Status: Alpha
      The VFC is a VME carrier for two VITA 57 (FMC) mezzanines. ...
    • VXS DSP FMC carrier
      A High Pin Count FMC carrier in VXS format with two Virtex 5 FPGAs plus a DSP on board....
  • Handheld measurement terminal
    It is a simple, low-cost measurement device equipped with GPS, GPRS modem, keyboard, display and LiOn battery. It can be also supplied/charged via a USB connector....
  • HDL Core Lib
    Project to share generic HDL cores....
    • AsyncArt
      Description The AsyncArt Project is comprised by a set of Open-Source HDL libraries targeted to the efficient implementation of clockless/asynchronous circuits over Commercial-Off-The-Shelf FPGA devices....
    • DDR3 controller for Spartan6
      • Status: Beta
      DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen....
    • EtherBone Core
      Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet. ...
    • FPGA Configuration Space
      This project defines data structures, to be embedded in the FPGA memory address space, to enumerate the devices that have been synthetized in the current design. The same structure is also used as a simple flash file system. AKA Self-Describing Bus (SDB) Specification for Logic Cores. The layout is simple enough to be parsed both by the host and by the internal soft-core, if any. ...
    • Gennum GN4124 core
      • Status: Release
      A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone. ...
    • IPBus
      IPBus is a FPGA Core that controls a Wishbone bus via Ethernet. Currently the transport protocol is UDP/IP, although there are plans for an ATA over Ethernet (AoE) implementation. There are reference designs for the SP601 and SP605 Xilinx FPGA boards....
    • LM32 processor
      • Status: Beta
      The LatticeMico32 processor is a Verilog core for a 6-stage pipelined RISC architecture. Originally designed for Lattice FPGAs, this project modifies it to support Altera and Xilinx. It has GNU toolchain support since gcc 4.5. This code is a fork of the milkymist fork of the original LM32 design....
    • Platform-independent core collection
      • Status: Planning
      A collection of platform-independent cores such as memories and synchronizer circuits....
    • QDR II controller for Virtex 6
      A QDR II RAM controller for the Virtex 6 FPGA family. This core is compliant with the Wishbone bus....
    • TDC core
      A Time to Digital Converter core for Spartan 6 FPGAs....
    • VME64x core
      A VHDL core for a VME64x slave. The other side behaves like a Wishbone master....
    • White Rabbit core collection
      • Status: Planning
      A collection of cores needed in the White Rabbit node and switch....
      • Software for White Rabbit PTP Core
        White Rabbit PTP Core software for LatticeMico32. It consists of a software wrapper for running a PTP daemon without an operating system and device drivers for WRPC HDL internals....
    • White Rabbit node core
      • Status: Planning
      A White Rabbit node core containing the WR PTP core, Etherbone, an embedded CPU, etc....
    • Wishbone Serializer Core
      • Status: Alpha
      A transparent Wishbone bridge between two FPGAs using high-speed serial links....
    • Wishbone slave generator
      • Status: Release
      wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:...
  • Level conversion circuits
    • Status: Planning
    The level conversion board project hosts a set of boards in VME form factor, with additional remote diagnostics/monitoring via I2C....
    • Conv TTL Blocking
      A level conversion board in VME64x form factor between TTL and Blocking Levels. Direction and levels are configurable. The project uses a Rear Transition Module for connectivity and a Front module with the active conversion and diagnostics electronics....
    • Conv TTL NIM 3in 30out
      • Status: Release
      A three-channel TTL to NIM (Nuclear Instrumentation Module) level conversion board in VME form factor....
    • Conv TTL RS485
      A level conversion board in VME64x double-height form factor between TTL and RS485. Direction and levels are configurable. The project uses a Rear Transition Module for connectivity and a Front module with the active conversion and diagnostics electronics....
  • Low-level RF Servo control
    A card used in CERN's Linac 3 for the control of the electromagnetic field inside RF accelerating cavities....
  • Miscellaneous Projects - non-HW
    Projects not directly identifiable with PCB or HDL core developments....
    • ADC Testing
      • Status: Release
      ADC testing procedures and software....
    • CERN BE-CO-HT contribution to Kicad
      This project hosts documentation and code to be contributed by CERN's BE-CO-HT section to the Kicad PCB design tool....
    • CERN LNGS Time Transfer
      A project to describe techniques and gather results of the time transfer between CERN and LNGS for the neutrino Time Of Flight experiment....
    • Electronics Design
      The Electronics Design project gives helpful entry points for electronics engineers. VHDL coding, design reviews, components, production, assembly and testing are some subjects....
    • FMC bus
      The FMC bus abstraction implements a Linux kernel bus named fmc. This allows to deal with FMC mezzanines in a carrier-independent way....
    • GTS (Guesses Timing Somehow)
      GTS is a tool which takes a binary for a given microprocessor (initially an LM32) and gives information about worst-case execution time....
    • Hdlmake
      • Status: Release
      Tool for generating multi-purpose makefiles for FPGA projects. ...
    • Libre Filter Design and Analysis Tool
      What is Libre-FDATool? Libre-FDATool is a Python package aimed to help the analysis and design of HDL filters from high-level specifications. It is Free/Libre Open Source Software....
    • PHASE
      PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor....
    • PMTLib
      The project is a set of Kicad Symbols and Footprints that are used in a collection of smaller Kicad based sub projects. Each sub project will use the common library to ease and standardise design but will be a related implementation or documentation of a design. The topic for the Library and designs are Photo Multiplier Tube (PMT) based particle and optical detectors....
    • Production Test Suite
      A software suite written in Python to help with production tests of PCBs....
    • ZIO
      A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware....
  • Neo51
    Neo51 is an open source hardware based on 89V51 microcontroller. It has a dual mode feature selectable via DIP switch supporting...
  • OHR Meta Project
    A meta project used to discuss and present information about Open Hardware and related subjects....
  • OHR Support
    • Status: Mature
    OHR project where you can get help and guidelines about OHR. It's a support project for questions/feedback and bugs....
  • OpenPicus
    OpenPicus is an Italian project made to fill the gap between Embedded Low Cost and Wireless. Picus modules are based on the well known Microchip PIC 24F 16bit processor connected to a Wireless Transceiver (WI-FI or BLUETOOTH). The OpenPicus Framework let you develop your Apps in easy way even without specific experience with Communication protocols....
  • ROBIN-NP
    • Status: Planning
    Hardware and firmware development of high-speed DAQ card for ATLAS TDAQ....
  • SFP ADC 130M 12b 1ch DAC 130M 12b 1cha
    Optical 130MS/s ADC/DAC with SFP - for digital transmission of analog signals over fibre....
  • SPI Boards Package
    SPI Boards Package is a set of electronic boards developed at Soleil Synchrotron (France). These boards can be connected together in a daisy chain and they communicate with an embedded controller via an SPI Bus. They provide the following features:...
    • SPICONTROLLER
      SPICONTROLLER is the controller board for the SPI Boards Package. It manage communication task with control system via Ethernet and with modular boards via SPI interface. Moreover, specific process can be embedded into the controller. ...
    • SPIETBOX
      SPIETBOX is a board developed around a SPARTAN-3 FPGA in order to process TTL and SSI encoders....
  • TimEX3
    The TimEX3 is a multipurpose compact PCI board designed to perform simple to medium complex logical functions....
  • Universal C64 Cartridge
    A C64 cartridge with USB connection for uploading CRT files from a PC and for fast turnaround time when developing assembler programs for the C64 on a PC. The board contains a MC9S08 microcontroller, a 128 kByte SRAM and a CPLD, which can be programmed to emulate many cartridge types. With a different firmware it can be used in standalone mode, without a C64, for other applications as well, like a logic analyzer or a motor controller....
  • VME ADC 250k 16b 36cha
    VME board with 36 ADC channels with a sampling rate of 250 kS/s and 16 bits resolution....
  • White Rabbit
    White Rabbit is a fully deterministic Ethernet-based network for general purpose data transfer and synchronization. It can synchronize over 1000 nodes with sub-ns accuracy over fiber lengths of up to 10 km. Commercially available....
    • Compact Universal Timing Endpoint based on White Rabbit
      A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC....
    • Distributed RF over White Rabbit
      This project deals with the distribution of RF signals over a White Rabbit network. In particular, it describes ways of extracting the characteristics of an RF signal (I/Q, Amplitude/Phase...) using a WR sampling node and the way to distribute those characteristics through Ethernet frames and generate the RF on the receiving nodes....
    • GSI Timing Starter Kit
      The GSI Timing Starter Kit is a functional snapshot of the eventual FAIR timing system, which is under active development. It demonstrates real-time coordination of two front-end equipment controllers. The product consists of a data master (Linux PC) which coordinates events, a timing master which synchronizes clocks (White Rabbit switch), and two front-end equipment controllers (either SPECv4 or SCUv2)....
    • PPSi
      A Precise Time Protocol (PTP, IEEE 1588) software stack whose single source code can be compiled for many architectures (POSIX systems, SPEC...) and which is easily extensible....
      • PTP noposix stack
        This is a port of an older Linux ptpd to support White Rabbit extensions and run both in hosted and freestanding environment. In the future we plan to replace it with PPSI, which has a much better design, but ptp-noposix is currently working pretty well despite being difficult to maintain....
    • White Rabbit Network Interface Card
      • Status: Beta
      A White Rabbit compliant Network Interface Card (NIC) based on the SPEC and the DIO FMC. This project hosts the HDL and associated software to configure the SPEC so it behaves as a NIC under the Linux OS....
    • White Rabbit Network Robustness
      The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered. ...
    • White Rabbit Standardization
      This project covers all efforts geared to standardize White Rabbit, with a view to providing a stable specification which everyone can use to build compliant products....
    • White Rabbit Starting Kit
      This project guides new users to start in the White Rabbit “World” with simple experiments. The starting kit uses two SPEC + FMC-DIO cards. Each node allows basic operations such as input timestamping or programmable output pulse generation. Additionally, specific software and gateware layers allow to use it as a standard network interface card implementing the White Rabbit technology functionalities....
    • White Rabbit Switch Hardware
      This project covers the hardware development of the White Rabbit switch....
    • White Rabbit Switch HDL
      This project contains all the HDL necessary for the FPGA of the WR switch....
    • White Rabbit Switch Software
      Development of software for the White Rabbit switch, and in particular the embedded Linux system running in the ARM9 processor....
    • White Rabbit Switch Testing
      A project to host all software and hardware developments related to testing the White Rabbit switch....

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