FMC Time to Digital Converter | FMC TDC 1ns 5cha

The FMC TDC 1ns 5cha Time to Digital Converter mezzanine board houses 5 input channels. It can calculate time differences between pulses arriving to the channels with a precision of ±700 ps.
It can be carried by any of the carrier boards: SPEC or SVEC. It is implemented using a dedicated time-to-digital converter chip from the European company ACAM.


SVEC carrier with two slots for TDC mezzanines and SPEC carrier with one slot for a TDC mezzanine (more TDC views )


Specifications

Input Channels 5 channels TTL with software selectable 50 Ohm termination.
Inputs need to be protected against +15V pulses with a pulse width of at least 10us at 50Hz
Channels enable Software controlled switch that enables/ disables all 5 channels
Timestamps buffer Circular buffer that keeps the last 128 pulses (256 rising and falling edges);
programmable interrupts implemented based on the number of accumulated timestamps or the amount of elapsed time
Timestamps precision (deviation) ± 700 ps
Timebase accuracy With White Rabbit: < 1ns
Without White Rabbit: ± 4 ppm from a local TCXO on the FMC card
Maximum input pulse rate 31.25 MHz from all 5 channels
Timestamps Timestamps apply to both rising and falling edges of incoming pulses;
on the software level the falling edges are only used for the calculation of the pulse width, ignoring pulses < 100 ns;
With White Rabbit, the TDC offers absolute timestamping and timestamps from different boards in the same White Rabbit network can be correlated.
Without White Rabbit the timestamps from one board need to be always subtracted between them, to calculate time differences
Minimum input pulse width 100 ns, narrower pulses are ignored on software level by subtracting a falling edge from the previous rising one
ACAM mode I-mode, 81ps resolution, +/- 500ps precision (6σ)
Connectors LEMO 00
FMC connector Low Pin Count
PCB 6 layers

Releases

The FMC TDC development consists of the following sub-projects; each sub-project has its corresponding release.

Link to Sub-project Description Release
Hardware Design of the TDC mezzanine board Hardware release EDA-02290
Gateware Associated gateware housed in the FPGA of the carrier Gateware release
Software Dedicated Linux software support Software release
Testing Long runs on the whole of the application (hw, gw, sw) and dedicated Production Test Suite and Calibration PTS release

Project documents

Link to document Description
Board Performance On precision and performance over time
Literature Relevant literature about Time to Digital conversion
Users Known users inside and outside CERN
CERN specific information -

Contacts

General Questions Erik van der Bij, Eva Gousiou at CERN
Commercial producers FMC TDC, Seven Solutions, Spain
BO-FMC-02290: FMC TDC 1ns, Janz Tec AG, Germany

Project Status

Date Event
06-12-2010 Project start
14-12-2010 First specification available for comments
09-03-2011 First schematic available. (need to replace LEDs)
18-03-2011 Second schematics design review held
08-04-2011 First layout made. Review made, needs moving of components (check review#1)
11-04-2011 Layout being modified. Planning: 3 assembled prototypes by 16 May
19-04-2011 New layout received. Design review on 20-04-2011
20-04-2011 Review held (check review#2 ); layout office modifies the design
29-04-2011 Layout office finalized the design
30-05-2011 Three prototypes ready
01-06-2011 Start of writing firmware
05-08-2011 Design specification review held (check review )
08-08-2011 Basic functionality OK. Several issues found that need a new PCB layout
16-12-2011 New PCB layout made. Production files will be generated
02-02-2012 V2 schematics and PCB made. Will be reviewed on 7 February. Foresee production 8 boards for 23 March.
07-02-2012 Schematics reviewed (check review#3 ); improved schematics ready by 21-02-2012 for new review
30-05-2012 V2 boards received
30-08-2012 V3 schematics and PCB being made; input circuit modified
23-10-2012 V3 schematics and PCB ready
15-11-2012 Ordered 60 V3 boards: 10 for delivery by begin March end April 2013, 50 by begin May 2013 (check order)
04-12-2012 Feedback on design received. Can use same PCB. Other changes may be handled in a V4
25-03-2013 Will make V3-1 design (only change of BOM) to handle five issues
08-04-2013 Working on: correcting two firmware bugs, writing documentation, writing software to test firmware
26-04-2013 No known firmware bugs left. Writing calibration test program
06-05-2013 V3-1 design ready (only change of BOM) to handle five issues
13-05-2013 CERN received 9 pre-series V3-1 boards
22-05-2013 CERN accepted quality of pre-series V3-1 boards;
production of 50 series (original foreseen for delivery in May 2013) started
09-08-2013 51 V3-1 boards received
20-06-2014 Added White Rabbit support for SVEC and SPEC
04-07-2014 Ordered 60 V3-1 boards: 20 for delivery by end October 2014, 40 by begin January 2015 (check order)
10-07-2014 Project split into hw, gw, sw sub-projects

Eva Gousiou | Javier Serrano | Erik van der Bij | 1 September 2014