FMC Time to Digital Converter | FMC TDC 1ns 5cha¶
The FMC TDC 1ns 5cha Time to Digital Converter mezzanine board houses 5 input channels. It can calculate time differences between pulses arriving to the channels with a precision of +-700 ps.
It can be carried by any of the carrier boards: SPEC or SVEC. It is implemented using a dedicated time-to-digital converter IC from the European company Acam chip in I-mode.
Linux software support for the board is available in the dedicated project FMC TDC SW.
The provided software comprises: Linux device driver based on ZIO and stacked on the SPEC or SVEC driver | User space libraries | Documentation.
|Input Channels|| 5 channels TTL with software selectable 50 Ohm termination.
Inputs need to be protected against +15V pulses with a pulse width of at least 10us at 50Hz
|Channels enable||Software controlled switch that enables/ disables all 5 channels|
|Timestamps buffer|| Circular buffer that keeps the last 128 pulses (256 rising and falling edges);
programmable interrupts implemented based on the number of accumulated timestamps or the amount of elapsed time
|Timestamps precision (deviation)||+/- 700 ps|
|Timebase accuracy||+/- 4 ppm from a local TCXO on FMC card; much better accuracy would be reached when used on a White Rabbit enabled FMC carrier|
|Maximum input pulse rate||31.25 MHz from all 5 channels|
|Timestamps|| Timestamps apply to both rising and falling edges of incoming pulses;
on the software level the falling edges are only used for the calculation of the pulse width, ignoring pulses < 100 ns;
the rising edges are always subtracted between them
|Minimum input pulse width||100 ns, narrower pulses are ignored on software level by subtracting a falling edge from the previous rising one|
|ACAM mode||I-mode, 81ps resolution, +/- 500ps precision (6σ)|
|FMC connector||Low Pin Count|
- Official production documentation (schematics, PCB, etc.):EDMS: EDA-02290|
- Developer's manual
- Board Performance
- CERN specific information
|Linux device drivers||Software release|
|14-12-2010||First specification available for comments.|
|09-03-2011||First schematic available. (need to replace LEDs)|
|18-03-2011||Second schematics design review held.|
|08-04-2011||First layout made. Review made, needs moving of components Review08042011.|
|11-04-2011||Layout being modified. Planning: 3 assembled prototypes by 16 May.|
|19-04-2011||New layout received. Design review on 20-04-2011.|
|20-04-2011||Review held Review20042011. Layout office modifies the design.|
|29-04-2011||Layout office finalised the design.|
|30-05-2011||Three prototypes ready.|
|01-06-2011||Start of writing firmware.|
|05-08-2011||Design specification review held. [[http://www.ohwr.org/documents/91]]|
|08-08-2011||Basic functionality OK. Several issues found that need a new PCB layout.|
|16-12-2011||New PCB layout made. Production files will be generated.|
|02-02-2012||V2 schematics and PCB made. Will be reviewed on 7 February. Foresee production 8 boards for 23 March.|
|07-02-2012||Schematics reviewed: (review07022012). Improved schematics ready by 21-02-2012 for new review.|
|30-05-2012||V2 boards received.|
|30-08-2012||V3 schematics and PCB being made. Input circuit modified.|
|23-10-2012||V3 schematics and PCB ready.|
|15-11-2012|| Ordered 60 V3 boards (10 for delivery by
|04-12-2012||Feedback on design received. Can use same PCB. Other changes may be handled in a V4.|
|25-03-2013||Will make V3-1 design (only change of BOM) to handle five issues.|
|08-04-2013||Working on: correcting two firmware bugs, writing documentation, writing software to test firmware.|
|26-04-2013||No known firmware bugs left. Writing calibration test program.|
|06-05-2013||V3-1 design ready (only change of BOM) to handle five issues.|
|13-05-2013||CERN received 9 pre-series V3-1 boards.|
|22-05-2013|| CERN accepted quality of pre-series V3-1 boards.
Production of 50 series (original foreseen for delivery in May 2013) started.
|09-08-2013||51 V3-1 boards received.|
Eva Gousiou | Javier Serrano | Erik van der Bij | 17 January 2014