Simple PCIe FMC carrier (SPEC)

Project description

The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an SFP connector. On the PCIe side it has a 4-lane interface, while the FMC mezzanine slot uses a low-pin count connector. This board is optimised for cost and is usable with most of the FMC cards designed within the OHR project (e.g. ADC cards, Fine Delay). The board is commercially available.

Labview and Linux drivers are available for the FMC DEL 1ns 4cha delay and FMC TDC 1ns 5cha TDC mezzanine cards.

Boards with a very similar architecture are available for the VME bus (SVEC - Simple VME FMC Carrier) and for the PXI Express bus (SPEXI - Simple PXI express FMC Carrier Board).
Other FMC projects and the FMC standard are described in FMC Projects.


SPEC 1.1 first prototype

Main Features

  • 4-lane PCIe (Gennum GN4124)
  • 1x Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C)
  • FMC slot with low pin count (LPC) connector
    • Vadj fixed to 2.5V
    • FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG
    • No dedicated clock signals from Carrier to FMC (only available on HPC pins)
  • Clocking resources
    • 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100 MHz (Silicon Labs Si570, freely usable)
    • 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
    • 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
    • 1x low-jitter frequency synthesizer (TI CDCM61004, fixed configuration, Fout=125 MHz, used by White Rabbit PTP core)
  • On board memory
    • 1x 2Gbit (256 MByte) DDR3 (MT41J128M16HA-15E)
    • 1x SPI 32Mbit flash PROM for multiboot FPGA powerup configuration, storage of the FPGA firmware or of critical data
  • Miscellaneous
    • on-board thermometer IC (DS18B20U+)
    • unique 64-bit identifier (DS18B20U+)
  • Front panel containing
    • 1x Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver (WhiteRabbit support). 1.25 and 2.5 Gbps.
    • Programmable Red and Green LEDs
    • FMC front panel
  • Internal connectors
    • 1x JTAG header for Xilinx programming during debugging
    • 2x SATA connector
    • 1x mini USB AB (USB-UART bridge)
  • FPGA configuration. The FPGA can optionally be programmed from:
    • GN4124 SPRIO interface (loaded by software driver at startup)
    • JTAG header
    • SPI 32Mbit flash PROM
    • selectable by GN4124 GPIO. Default option would be loading via the SPI flash PROM (stand-alone applications).
  • Stand-alone features
    • External 12V power supply connector
    • mini USB connector
    • 4 LEDs
    • 2 buttons
  • Power consumption: 5-12 Watt, depending on application
  • Optimised for cost
    • 6-layer PCB

Project information


Releases


Contacts

Commercial producers

General questions about project


Status

Date Event
22-06-2010 Start of project. Design is done by an external company, based on the FMC PCIe Carrier.
Reviewing will be done by CERN.
29-06-2010 Main features reviewed by JS, PA, MC & EB. Design can start.
12-07-2010 First schematics published. Ready for review.
10-09-2010 Review comments integrated. Start of PCB layout.
05-10-2010 PCB layout review held.
05-11-2010 Design finished.
19-01-2011 Three prototypes arrived at CERN.
18-04-2011 First V1.1 prototypes received, start testing them.
01-07-2011 Three V2 boards received. One fully tested OK. Two only shortly tested.
17-07-2011 Order placed for 70 SPEC cards at Seven Solutions.
23-08-2011 V4 released. Solves a minor mechanical problem with the SFP connector.
14-03-2012 CERN accepted the 10 preseries boards that were received on 7 March.
12-06-2012 SPEC boards passed most restrictive EMC tests for industrial and domestic classes. Test report.
13-06-2012 Board available from three commercial producers.
03-12-2013 Labview Driver available for FMC DEL 1ns 4cha and FMC TDC 1ns 5cha.

Complete status


Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 28 July 2014

spec.JPG (121 kB) Tomasz Wlostowski, 2010-12-22 18:30

spec_v2.jpg (103.8 kB) Tomasz Wlostowski, 2011-03-07 15:45

spec_v1.1_top.JPG (55.9 kB) Matthieu Cattin, 2011-04-18 15:16

spec_v1.1_bottom.JPG (52.6 kB) Matthieu Cattin, 2011-04-18 15:17

SPEC_top_high_res.jpg (1 MB) Javier Serrano, 2011-04-29 10:09

SPEC_bottom_high_res.jpg (1.3 MB) Javier Serrano, 2011-04-29 10:10