Review25042012comments

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SVEC schematics review 25.04.2012
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MEETING SUMMARY

  + DATE           25.04.2012  15:30 - 16:30 
  + PLACE          CERN Prevessin, Building 864, Room 1-A15
  + SUBJECT        SVEC Review
  + SVN            http://svn.ohwr.org/svec/trunk/circuit_board/SVEC  
  + REVISION       13
  + PARTICIPANTS: 
      Van der Bij, Erik          EVB    Erik.van.der.Bij@cern.ch 
      Cattin, Matthieu           MC     matthieu.cattin@cern.ch    
      Wlostowski, Tomasz         TW     tomasz.wlostowski@cern.ch         
      Gil Soriano, Carlos        CGS    carlos.gil.soriano@cern.ch  
  + SUMMARY
    There are still some errors from previous review:
      -+ SCHEMATICS
        Check out the USB interface and tidy up all the project.
      -+ LAYOUT
        Special attention should be taken to the SATA connector cutouts.
        Tidy up needed.
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                    |         ! : fatal                 |  
                    |         + : important             |  
                    |         - : minor                 |   
                    |         ? : question              |  
                    |         * : note                  |  
                    |         A : already               |  
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===============================================================================
SCHEMATICS

+ SVEC_TOP.SchDoc
--+ AFPGA.SchDoc
--+ AFPGA_power.SchDoc
--+ DDR3.SchDoc
--+ DDR3_2.SchDoc
--+ FPGA_GTP.SchDoc
--+ JTAG Chain + SFPGA Flash.SchDoc
--+ SFPGA.SchDoc
--+ SFPGA_power.SchDoc
--+ USB Interface.SchDoc
--+ FMC_connectors.SchDoc
--+ VME_Connectors.SchDoc
--+ Front_panel.SchDoc
--+ Power_supplies.SchDoc
--+ Clk_generation.SchDoc

--> BOM
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General:
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[EVB]  A- Frames should be recheck, still bad namings
fixed
[MC]   A- Use consitant naming convention for file names.\
ok, done, the name starts from capital letter, only abbreviation have capital letters
[MC]   A- Different sheets size.
it took realy lot of time but now all sheets are A3

[MC]   *  Re-annotation should be avoided during the review process.
          It makes hard to track changes from preview review comment,
          often based on component designator!
[MC]   -  Add a red dashed square around unmounted components (c.f. USB_connector.SchDoc).
done
[MC]   A- Bad naming in the sheets
fixed
[MC]   +  Add dashed lines around components that are not mounted.
[CGS]  *  PowerSupplies.Txt is not yet uploaded to repo.
OK
[CGS]  -  VME_RETRY should be labeled as VME_RETRY_N
done
[CGS]  -  VME_BERR should be labeled as VME_BERR_N
done
[CGS]  +  The updated schematic PDF is missing. Generate and upload.
it was in "files" section

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SVEC_TOP.SchDoc
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[MC]   +  Bad lines for division, bad letters,...
[MC]   -  Red text describing the blocks is sometimes to small (e.g. "SFP gigabit port").
[MC]   -  I'd put AFPGA and SFPGA with a big (bold) font to clearly identify them.
[MC]   -  Unify line style to split the blocks (pink line, double blue lines).
          I'd put a single blue line everywhere.
OK, done
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AFPGA.SchDoc
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[MC]   +  LA_18 (FMC1) should be connected to the other half-bank (LA_17 to LA_33).
you are right!
[TW]   A+ R212 R240 what for?

it was used to match 3.3V FPGA output to FMC circuit supplied from 2.5V. 
At least in my designs I connected this line to the IO of the FPGA on the FMC
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Clk_generation.SchDoc
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[MC]  ?  What is the comment box under IC12 (CDCM61004RHBT) for?
         Should be removed
ok, it wasjust to remind the IC settings

[MC]  +  Display OSC3 part number.
[TW]  A+ 100 ohm resistors what for?
it is part of Optional RC filter for 1-bit DAC from FPGA output.
Can be used to fine tune Si571, which has a control voltage input.

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DDR3.SchDoc
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[MC]  -  Duplicated DDR_A, DDR_DQ and DDR_BA buses.
         Remove the one under IC19H (Bank4).
ok
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DDR3_2.SchDoc
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[MC]  -  Duplicated DDR_A, DDR_DQ and DDR_BA buses.
         Remove the one under IC19H (Bank4).
ok
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FPGA_GTP.SchDoc
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[MC]  -  Change "SATA connectors" to "eSATA connectors".
done
[MC]  -  Use the same color for the text like "SATA connector", "Staight"... (c.f. FMC_connector.SchDoc).
ok
[CGS] ? Maybe we can add directives to traces with the same length (AF12, AF14)in IC19L
ok
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JTAG Chain + SFPGA Flash.SchDoc
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[MC]  -  The comment box "SFPGA configuration mode ..." is touching the ports.
         Move it a bit to the right.
ok
[MC]  +  Change serial termination resistors to smaller values, to match the traces impedance.
OK, I changed R274, R259, R260 but rest of them limit the current during 3.3V-> 2.5V conversion
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SFPGA.SchDoc
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[MC]  -  License frame is shifted compared to the text.
fixed
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USB Interface.SchDoc
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[MC]  !  IC17 power supplies are badly connected.
         VIO must be connected to P3V3.
         GND and EP must be connected to GND.
that's true, no idea why the pins were shifted.

[CGS] !  IC17, pins 2, 14, 15: GND is floating!
[CGS] !  IC17, pin 29 must be grounded.
[CGS] !  IC17, pin 5: VIO should be set to something.
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FMC_connectors.SchDoc
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[TW]  A+ FMC1_PGC2M lines (pin D1) - it's an input to the FMC. What's 4K7 series for?
current limit for 3.3V-> 2.5V input of the circuit at the FMC board supplied from 2.5V.
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VME_Connectors.SchDoc
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[EVB] !  Remove JTAG lines. Are they used?
no idea, they were connected in VFC board so I simply left them.

[MC]  -  License text box is outside of the sheet frame.
no, it is not. ALtium scales the text depend how you display it.

[MC] A+  *_DIR pullups
there is already one on VME_A_OE_N but OK, I added it here as well

[MC]  +  VME_IACKIN_N connection through R209. What for?
it is when FPGA is not initialized and the IACK signal may then be bypassed by the R209
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Front_panel.SchDoc
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[MC]  -  Wires color of the ESD discharge circuit is different.
you have got very good sight:)
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Power_supplies.SchDoc
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[MC]  + Use only one name per power rail.
        Change P12V_FMC1 and P12V_FMC2 to P12V_FMC.
        Change P2V5_FMC1 and P2V5_FMC2 to P2V5_FMC.
ok
[MC]  - In comment box "DC/DC calulation...", an 'A' is missing after some ILpeak value.
ok
[MC]  - In comment box "Power estimation...", it's writen "HPC -4A, LPC -2A".
        The '-' sign should be removed or replaced by '=' to avoid confusion.
ok
[MC]  - PowerSupplies.Txt is missing in the repo.
[CGS] * IC18. I have checked out its values and it is OK.
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BOM
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[CGS] ? Can we get rid of 7K5 resistors? Only five in BOM
can be difficult, it's hard to combine existing resistors to get division ratios for rest of the voltages
[CGS] ? Same for R183 and R169. 12V has a lot of margin in the compensation.
yes, I know, but still need any resistor with several tens of kOhm. Otherwise would need to add capacitors of a few nF
I calculated all possible value combinations and placed them in txt file.
[CGS] ? R232 is the only 12K resistor. Can it be replaced and removed from BOM?
well it must be 1% value required by the manufacturer of the FTDI chip. It is not mounted by default anyway
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===============================================================================
LAYOUT
===============================================================================
[MC]  + A few DDR traces on the bottom are still crossing the plane on L9.
ok, fixed
[MC]  + Copper islands between traces.
        Remove polygon fill on signal layers.
OK, just wanted to make sure that the copper density will be similar on all layers.

[MC]  ! P5V_VME polygon is almost cut by the power_SATA connector cutout on L4.
OK, fixed

[MC]  ! The power_SATA connector cutout will be useless as it is.
        It should go until the edge of the board. => not possible with the VME ESD circuit!!!
the idea was to simply cut the PCB when necesarry - I removed the copper in that place.
For stand-alone operation we don't need ESD anyway

[MC]  - P1V5 polygon doesn't have to go that far down on L9.
it needs - the LVDS lines like ot have continous planes around
here we don't gain anything having it smalled

[MC]  + P12V_FMC is almost cut by H4 and H7 on Bottom layer.
well, could be done better, fixed

[MC]  - There is a few overlapping designators (e.g. C176 and R320), and designator on vias.
strange that Altium didn't find that! The rule is set.
In case of vias, they are small and masked so don't affect the silk screen seriously
[MC]  + Add test points (unmounted) for every power rail.
they are already ones!

[MC]  ! polygon connect is too small for components on power rails!
ok, changed to 7 mils
but note, the length of the connection is really small, about 5..6 mils
since we usually have 4 such connectors, it gives 20 mils x5 mils track, its resistance is neglidgible

[MC]  - Use the same font and size for all silkscreen text. 'Sherif sans' is prefered.
it would be difficult - in case of designators I cannot use bigger, I used the same as in case of SPEC.
In case of connector and other descriptions we want them to be clearly visible.

[MC]  + DDR_DQ15 trace has an antenna on Top layer.
you are right, wander why Altium didn't find that

[MC]  ! P12V_FMC is connected to slot 2 with only one via!
you are right, that's the effect of strange behaviour of algorithm that automatically removes loops, fixed

[MC]  + There is only one P12V_FMC decoupling capacitor for slot 2 (three for slot 1).
not really, there are 2 other ones on the other side.

[MC]  * We should place one via per pin to connect the FMC connector power supplies.
it was my original idea, but Altum removed them. Now I place polygons and vias - they are not affected by the loop removal feature

[MC]  - Board reference should be moved to a corner.
done

[MC]  ? What is the text "PO VME" on the bottom? It should be removed.
ok

[MC]   ! Remove fills in signal layers
OK, but don't be surprized when the board bends :)

[MC]   ! SATA connector cutout should be solved. Not possible to cut up there.
why? Of course I can shift it to the edge or make bigger cutout, but there would be difficulty in installing it in the VME crate.
I would simply leave it as it is and when stand-alone operation is needed, simply cut the PCB as is marked on the top overlay.
 removed the copper to make it easier.

[TW]   + FMC1_LA_N0 not enough spacing with adjacent lines.
Ok, I can switch to another layer
[CGS]  * Board Thickness is 59.055 mils. VME standard 1.6 mm. OK
[CGS]  - TOP:       P2V5 island could be parallel to P2V5_FMC1
ok, just cosmetics, fixed :)

[CGS]  ! L4 PWR3.3: Why P5V_VME is splitted into the big one and a small island close to STA connector?
fixed
[CGS]  ? L9 PWR:    Same for P3V3
ok

[CGS]  * PLL_2SFPGA_PN is long. Is it critical?
don't think so, it is not going to be high frequency, probably we will never need this clock.

[CGS]  * L3:   Islands in the way of SATA to FPGA
[CGS]  * L3:   Islands in the way of FMC1 to FPGA
removed
[CGS]  * HSLs seem well equalized