Core description¶
The VME64x core implements a VME64 slave on one side and a WishBone master on the other with FIFOs in-between.
The core supports SINGLE, BLT, MBLT, 2eVME and 2eSST transfers in A24, A32 and A64 address modes and D08 (OE), D16, D32, D64 data transfers with unaligned data types (only D64 for 2eVME and 2eSST). Lock command ADOH cycles are supported.
The core can be configured via implemented CR/CSR configuration space with support for external configuration ROM and configuration RAM.
A ROACK type IRQ controller with one interrupt input and a programmable interrupt level and Status/ID register is provided.
A WishBone side features a classic WB master for SINGLE, BLT and MBLT transfers and a modified WB master for 2eVME and 2eSST transfers, which was designed to be used with a pipeline on the WB bus.
Project Status¶
| Date | Event |
|---|---|
| 01-04-2010 | Start working on project. |
| 25-05-2010 | First HDL release. |
| 10-02-2011 | First register read/write made with the core on the VFC. |
| 01-02-2012 | New student will work full time on project. |
| 03-05-2012 | Core has been modified to implement CSR space. CSR and single R/W working on VFC V2. |
| 10-05-2012 | Working on BLT, MBLT and 2eSST implementation. |
Erik van der Bij - 10 May 2012