Description

The Wishbone serializer core helps to solve the problem of accessing a Wishbone slave in one Xilinx Spartan 6 FPGA from a Wishbone master in another Spartan 6 in a transparent way. Both FPGAs are connected by two Xilinx Gb serial links, one in each direction. In order to cope with the high latency and still maintain a good throughput, Wishbone pipelined access mode is used. The main usage would be for use on the VFC VME FMC carrier board.

This project is on hold.


Documentation


Status

Date Event
01-10-2010 Project start.
12-11-2010 Technical Specification published (order).
15-12-2010 Order for development placed.
07-01-2011 Start learning on Xilinx Aurora protocol
21-01-2011 Test Aurora protocol using two boards sp605
23-02-2011 First version ready using burst cycles
16-04-2012 Sent VFC to Seven Solutions for testing the core (order).
05-06-2012 Core working on VFC at Seven Solutions. Documentation written.
01-11-2012 Additional tests at CERN show that no flow control is implemented, loosing data in certain circumstances.
04-12-2012 Project on hold. Not needed for SVEC carrier and users of VFC have other solutions.

Javier Serrano, Erik van der Bij - 21 December 2012

block-RXTX_small.png (40.9 kB) Javier Serrano, 2010-11-14 20:12

Test_vme64x_WBserializer.png (60.9 kB) Davide Pedretti, 2012-10-18 18:50

ChipScope_wbserializer_bug.jpg (109.9 kB) Davide Pedretti, 2012-10-18 18:52