Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
A
Absolute Encoder VHDL core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Absolute Encoder VHDL core
Commits
6d4e5e3f
Commit
6d4e5e3f
authored
Nov 18, 2015
by
Fabien Le Mentec
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
fix: check data_len to fix questasim failure
parent
c7eaeeb6
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
15 additions
and
1 deletion
+15
-1
absenc_utils.vhd
src/absenc_utils.vhd
+15
-1
No files found.
src/absenc_utils.vhd
View file @
6d4e5e3f
...
...
@@ -211,7 +211,21 @@ signal is_signed: std_logic;
begin
is_signed
<=
data_in
(
to_integer
(
data_len
)
-
1
)
when
(
data_len
>
0
)
else
'0'
;
process
(
data_in
,
data_len
)
begin
-- fixme: modelsim fails without this check
-- synthesis translate_off
is_signed
<=
'0'
;
if
data_len
>
0
then
-- synthesis translate_on
is_signed
<=
data_in
(
to_integer
(
data_len
)
-
1
);
-- synthesis translate_off
end
if
;
-- synthesis translate_on
end
process
;
process
(
is_signed
,
data_in
)
begin
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment