Commit 49e7f56f authored by Fernando Cambauva's avatar Fernando Cambauva

New folder and files structure

structure following the pattern DIG
parent e483ceef
# Altium files
# History:
*History
*_Previews
*.LOG
*Project Outputs*
*Project Logs*
*gerbers*
*.outjob
*.prjPcbStructure
*.Dat
*.PcbLib
# Windows image file caches
Thumbs.db
ehthumbs.db
# Folder config file
Desktop.ini
# Recycle Bin used on file shares
$RECYCLE.BIN/
# Windows Installer files
*.cab
*.msi
*.msm
*.msp
# Windows shortcuts
*.lnk
# =========================
# Operating System Files
# =========================
# OSX
# =========================
.DS_Store
.AppleDouble
.LSOverride
# Thumbnails
._*
# Files that might appear on external disk
.Spotlight-V100
.Trashes
# Directories potentially created on remote AFP share
.AppleDB
.AppleDesktop
Network Trash Folder
Temporary Items
.apdisk
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This source diff could not be displayed because it is too large. You can view the blob instead.
This diff is collapsed.
This source diff could not be displayed because it is too large. You can view the blob instead.
T = 0.018mm (3 mils Clearnce min = 0.076mm)
Er = 4.7...4.2
Liczone dla Er=4.4 (zakres er = 4.7 ... 4.2 - gdzie dla GHz jest 4.2m a dla kHz 4.7)
SE50
TOP & BTM
Microstip
h = 0.11mm
W:
[mm] 0.1 0.125 0.15 0.175
[mils] 4 5 6 7
SE 68 62 56 51
Internal L1 L2 L3 L4
Asymmetric Stripline
h = 0.1mm
h1 = 0.11mm
W:
[mm] 0.075 0.09 0.1 0.125
[mils] 3 3.5 4 5
SE 54 50 47 42
####################
SE60DE100
TOP & BTM
Microstip
h = 0.11mm
W-GAP:
[mm] 0.075-0.075 0.1-0.1 0.1-0.075 0.125-0.1 0.15-0.125 0.15-0.15 0.175-0.125
[mils] 3-3 4-4 4-3 5-4 6-5 6-6 7-5
SE-DE 76-115 68-109 68-103 62-100 56-95 56-98 51-86
Internal L1 L2 L3 L4
Asymmetric Stripline
h = 0.1mm
h1 = 0.11mm
H = 0.21mm
W:
[mm] 0.075-0.075 0.075-0.1 0.08-0.125 0.08-0.145 0.1-0.1 0.1-0.125 0.125-0.15 0.15-0.15 0.125-0.175
[mils] 3-3 3-4 3.15-5 3.15-5.7 4-4 4-5 5-6 6-6 5-7
SE-DE 54-93 54-97 53-98 53-99 47-85 47-88 42-80 38-72 42-81
-----------------------------------------------------------------
DDR_SE_OUTER_LAYER = MICROSTRIP width 0.175mm = 51 Ohm
DDR_SE_MID_LAYER = Asymmetric Stripline width 0.125 mm = 42 Ohm
DDR_DE_OUTER_LAYER = MICROSTRIP width/GAP 0.175mm/0.125mm = 51_SE/81_DE
DDR_DE_MID_LAYER = Asymmetric Stripline width/GAP 0.125mm/0.175mm = 42_SE/81_DE
SINGLE_ENDED_OUTER_LAYER = MICROSTRIP width 0.175mm = 51 Ohm
SINGLE_ENDED_MID_LAYER = Asymmetric Stripline width 0.09 mm = 50 Ohm
DIFFERENTIAL_OUTER_LAYER = MICROSTRIP width/GAP 0.15mm/0.15mm = 56_SE/98_DE
DIFFERENTIAL_MID_LAYER = Asymmetric Stripline width/GAP 0.08mm/0.145mm = 53_SE/99_DE
---------------------------------------- 18um additonal galvanic plating
DDR_SE_OUTER_LAYER = MICROSTRIP width 0.16mm = 50 Ohm
DDR_DE_OUTER_LAYER = MICROSTRIP width/GAP 0.165mm/0.135mm = 49_SE/83_DE
SINGLE_ENDED_OUTER_LAYER = MICROSTRIP width 0.16mm = 50 Ohm
DIFFERENTIAL_OUTER_LAYER = MICROSTRIP width/GAP 0.13mm/0.17mm = 56_SE/99_DE
PORT2=RX2_P,RX2_N,TX2_N,TX2_P
PORT3=RX3_P,RX3_N,TX3_N,TX3_P
AMC_ADD=GA0,GA1,GA2
AMC_FABRIC_CLOCK=FCLKA_N,FCLKA_P
AMC_JTAG=TCK,TDI,TDO,TMS,TRST#
AMC_TELECOM_CLOCK=TCLKA_N,TCLKA_P,TCLKB_N,TCLKB_P,TCLKC_N,TCLKC_P,TCLKD_N,TCLKD_P
FAT_PIPE1=RX4_P,RX4_N,TX4_N,TX4_P,RX5_P,RX5_N,TX5_N,TX5_P,RX6_P,RX6_N,TX6_N,TX6_P,RX7_P,RX7_N,TX7_N,TX7_P
FAT_PIPE2=RX8_P,RX8_N,TX8_N,TX8_P,RX9_P,RX9_N,TX9_N,TX9_P,RX10_P,RX10_N,TX10_N,TX10_P,RX11_P,RX11_N,TX11_N,TX11_P
I2C=SCL,SDA
MLVDS=RX17_P,RX17_N,TX17_N,TX17_P,RX18_P,RX18_N,TX18_N,TX18_P,RX19_P,RX19_N,TX19_N,TX19_P,RX20_P,RX20_N,TX20_N,TX20_P
PORT0=RX0_P,RX0_N,TX0_N,TX0_P
PORT1=RX1_P,RX1_N,TX1_N,TX1_P
PORT2=RX2_P,RX2_N,TX2_N,TX2_P
PORT3=RX3_P,RX3_N,TX3_N,TX3_P
[DesignatorManager]
[SheetNumberManager]
SheetNumberOrder=Display Order
SheetNumberMethod=Increasing
This diff is collapsed.
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=AMC_CON|SchDesignator=AMC_CON|FileName=AMC_Connector.SchDoc|SymbolType=Normal|RawFileName=AMC_Connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=ASATA|SchDesignator=ASATA|FileName=AMC-SATA.SchDoc|SymbolType=Normal|RawFileName=AMC-SATA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=Block schematic|SchDesignator=Block schematic|FileName=block schematic.SchDoc|SymbolType=Normal|RawFileName=block schematic.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=CLK_MGT|SchDesignator=CLK_MGT|FileName=Clock_management.SchDoc|SymbolType=Normal|RawFileName=Clock_management.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=FPGA|SchDesignator=FPGA|FileName=FPGA.SchDoc|SymbolType=Normal|RawFileName=FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=HeightUnderFMC|SchDesignator=HeightUnderFMC|FileName=HeightRuleRoom1.9mm.SchDoc|SymbolType=Normal|RawFileName=HeightRuleRoom1.9mm.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=HPC1|SchDesignator=HPC1|FileName=FMC_connector.SchDoc|SymbolType=Normal|RawFileName=FMC_connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=HPC2|SchDesignator=HPC2|FileName=FMC_connector.SchDoc|SymbolType=Normal|RawFileName=FMC_connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=IPMI|SchDesignator=IPMI|FileName=IPMI.SchDoc|SymbolType=Normal|RawFileName=IPMI.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=JTAG_CONF|SchDesignator=JTAG_CONF|FileName=JTAG_Configuration.schdoc|SymbolType=Normal|RawFileName=JTAG_Configuration.schdoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=LVDS_PHY|SchDesignator=LVDS_PHY|FileName=M-LVDS PHY.SchDoc|SymbolType=Normal|RawFileName=M-LVDS PHY.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=PWR_MGT|SchDesignator=PWR_MGT|FileName=POWER_Management.SchDoc|SymbolType=Normal|RawFileName=POWER_Management.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=RTM_CON|SchDesignator=RTM_CON|FileName=RTM_CON.SchDoc|SymbolType=Normal|RawFileName=RTM_CON.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=SDRAM|SchDesignator=SDRAM|FileName=SDRAM.SchDoc|SymbolType=Normal|RawFileName=SDRAM.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=UUART|SchDesignator=UUART|FileName=USB_UART.SchDoc|SymbolType=Normal|RawFileName=USB_UART.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FHPC1|SchDesignator=FHPC1|FileName=FMC_HPC1.SchDoc|SymbolType=Normal|RawFileName=FMC_HPC1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FHPC2|SchDesignator=FHPC2|FileName=FMC_HPC2.SchDoc|SymbolType=Normal|RawFileName=FMC_HPC2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FMGT|SchDesignator=FMGT|FileName=FPGA_MGT.SchDoc|SymbolType=Normal|RawFileName=FPGA_MGT.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA_SUP|SchDesignator=FPGA_SUP|FileName=FPGA_SUP.SchDoc|SymbolType=Normal|RawFileName=FPGA_SUP.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FSDRAM|SchDesignator=FSDRAM|FileName=FPGA_SDRAM.SchDoc|SymbolType=Normal|RawFileName=FPGA_SDRAM.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=IPMI.SchDoc|Designator=CPU|SchDesignator=CPU|FileName=CPU.SchDoc|SymbolType=Normal|RawFileName=CPU.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=IPMI.SchDoc|Designator=RTCE|SchDesignator=RTCE|FileName=RTCE.SchDoc|SymbolType=Normal|RawFileName=RTCE.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=IPMI.SchDoc|Designator=THERMO|SchDesignator=THERMO|FileName=Thermometers.SchDoc|SymbolType=Normal|RawFileName=Thermometers.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=IPMI.SchDoc|Designator=UUART|SchDesignator=UUART|FileName=USB_UART.SchDoc|SymbolType=Normal|RawFileName=USB_UART.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_10|SchDesignator=SUP_10|FileName=SUP_1V.SchDoc|SymbolType=Normal|RawFileName=SUP_1V.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_12_18|SchDesignator=SUP_12_18|FileName=SUP_1.2_1.8.SchDoc|SymbolType=Normal|RawFileName=SUP_1.2_1.8.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_15|SchDesignator=SUP_15|FileName=SUP_1.5_3.3.SchDoc|SymbolType=Normal|RawFileName=SUP_1.5_3.3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_HPC25|SchDesignator=SUP_HPC25|FileName=SUP_2.5_FMC.SchDoc|SymbolType=Normal|RawFileName=SUP_2.5_FMC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_HPC33|SchDesignator=SUP_HPC33|FileName=SUP_3.3_FMC.SchDoc|SymbolType=Normal|RawFileName=SUP_3.3_FMC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=UI|SchDesignator=UI|FileName=UI_mon.SchDoc|SymbolType=Normal|RawFileName=UI_mon.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Clock_management.SchDoc|Designator=CLK_WR|SchDesignator=CLK_WR|FileName=Clock_WR.SchDoc|SymbolType=Normal|RawFileName=Clock_WR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Clock_management.SchDoc|Designator=FCLK|SchDesignator=FCLK|FileName=FMC_Clocks.SchDoc|SymbolType=Normal|RawFileName=FMC_Clocks.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=TopLevelDocument|FileName=AMC_FMC_Carrier.SchDoc
[OutputJobFile]
Version=1.0
[OutputGroup1]
Name=
Description=
TargetOutputMedium=PDF
VariantName=[No Variations]
VariantScope=0
CurrentConfigurationName=
TargetPrinter=Brother DCP-J315W Printer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputMedium1=Print Job
OutputMedium1_Type=Printer
OutputMedium1_Printer=
OutputMedium1_PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputMedium2=PDF
OutputMedium2_Type=Publish
OutputMedium3=Folder Structure
OutputMedium3_Type=GeneratedFiles
OutputMedium4=Video
OutputMedium4_Type=Multimedia
OutputType1=Schematic Print
OutputName1=Schematic Prints
OutputCategory1=Documentation
OutputDocumentPath1=
OutputVariantName1=
OutputEnabled1=1
OutputEnabled1_OutputMedium1=0
OutputEnabled1_OutputMedium2=1
OutputEnabled1_OutputMedium3=0
OutputEnabled1_OutputMedium4=0
OutputDefault1=0
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=0.98|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
Configuration1_Name1=OutputConfigurationParameter1
Configuration1_Item1=Record=SchPrintView|ShowNoERC=True|ShowParamSet=True|ShowProbe=True|ShowBlanket=True|NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle|ShowNote=True|ShowNoteCollapsed=True|ExpandDesignator=True|ExpandNetLabel=False|ExpandPort=False|ExpandSheetNum=False|ExpandDocNum=False|PrintArea=0|PrintAreaRect.X1=0|PrintAreaRect.Y1=0|PrintAreaRect.X2=0|PrintAreaRect.Y2=0
OutputType2=PCB Print
OutputName2=PCB Prints
OutputCategory2=Documentation
OutputDocumentPath2=AMC_FMC_Carrier_35u.PcbDoc
OutputVariantName2=
OutputEnabled2=1
OutputEnabled2_OutputMedium1=0
OutputEnabled2_OutputMedium2=2
OutputEnabled2_OutputMedium3=0
OutputEnabled2_OutputMedium4=0
OutputDefault2=0
PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=0.84|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
Configuration2_Name1=OutputConfigurationParameter1
Configuration2_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView
Configuration2_Name2=OutputConfigurationParameter2
Configuration2_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False
Configuration2_Name3=OutputConfigurationParameter3
Configuration2_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
Configuration2_Name4=OutputConfigurationParameter4
Configuration2_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
Configuration2_Name5=OutputConfigurationParameter5
Configuration2_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
Configuration2_Name6=OutputConfigurationParameter6
Configuration2_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
Configuration2_Name7=OutputConfigurationParameter7
Configuration2_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical8|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
Configuration2_Name8=OutputConfigurationParameter8
Configuration2_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
Configuration2_Name9=OutputConfigurationParameter9
Configuration2_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
Configuration2_Name10=OutputConfigurationParameter10
Configuration2_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
[PublishSettings]
OutputFilePath2=C:\Users\Greg\Documents\DESIGNS\BPM-DBE\PCB_uTCA_FMC_Carrier\
ReleaseManaged2=0
OutputBasePath2=C:\Users\Greg\Documents\DESIGNS\BPM-DBE\PCB_uTCA_FMC_Carrier\
OutputPathMedia2=
OutputPathOutputer2=[Output Type]
OutputFileName2=AMC_FMC_Carrier.pdf
OpenOutput2=1
PromptOverwrite2=1
PublishMethod2=0
ZoomLevel2=80
FitSCHPrintSizeToDoc2=0
FitPCBPrintSizeToDoc2=0
GenerateNetsInfo2=1
MarkPins2=1
MarkNetLabels2=1
MarkPortsId2=1
GenerateTOC=1
OutputFilePath3=
ReleaseManaged3=1
OutputBasePath3=
OutputPathMedia3=
OutputPathOutputer3=[Output Type]
OutputFileName3=
OpenOutput3=1
OutputFilePath4=
ReleaseManaged4=1
OutputBasePath4=
OutputPathMedia4=
OutputPathOutputer4=[Output Type]
OutputFileName4=
OpenOutput4=1
PromptOverwrite4=1
PublishMethod4=5
ZoomLevel4=50
FitSCHPrintSizeToDoc4=1
FitPCBPrintSizeToDoc4=1
GenerateNetsInfo4=1
MarkPins4=1
MarkNetLabels4=1
MarkPortsId4=1
MediaFormat4=Windows Media file (*.wmv,*.wma,*.asf)
FixedDimensions4=1
Width4=352
Height4=288
MultiFile4=0
FramesPerSecond4=25
FramesPerSecondDenom4=1
AviPixelFormat4=7
AviCompression4=MP42 MS-MPEG4 V2
AviQuality4=100
FFmpegVideoCodecId4=13
FFmpegPixelFormat4=0
FFmpegQuality4=80
WmvVideoCodecName4=Windows Media Video V7
WmvQuality4=80
[GeneratedFilesSettings]
RelativeOutputPath2=C:\Users\Greg\Documents\DESIGNS\BPM-DBE\PCB_uTCA_FMC_Carrier\
OpenOutputs2=1
RelativeOutputPath3=
OpenOutputs3=1
AddToProject3=1
TimestampFolder3=0
UseOutputName3=0
OpenODBOutput3=0
OpenGerberOutput3=0
OpenNCDrillOutput3=0
OpenIPCOutput3=0
EnableReload3=0
RelativeOutputPath4=
OpenOutputs4=1
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=AMC_CON|SchDesignator=AMC_CON|FileName=AMC_Connector.SchDoc|SymbolType=Normal|RawFileName=AMC_Connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=ASATA|SchDesignator=ASATA|FileName=AMC-SATA.SchDoc|SymbolType=Normal|RawFileName=AMC-SATA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=CLK_CROSSBAR|SchDesignator=CLK_CROSSBAR|FileName=Clock_management.SchDoc|SymbolType=Normal|RawFileName=Clock_management.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=FPGA|SchDesignator=FPGA|FileName=FPGA.SchDoc|SymbolType=Normal|RawFileName=FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=HPC1|SchDesignator=HPC1|FileName=FMC_connector.SchDoc|SymbolType=Normal|RawFileName=FMC_connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=HPC2|SchDesignator=HPC2|FileName=FMC_connector.SchDoc|SymbolType=Normal|RawFileName=FMC_connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=IPMI|SchDesignator=IPMI|FileName=IPMI.SchDoc|SymbolType=Normal|RawFileName=IPMI.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=JTAG_CONF|SchDesignator=JTAG_CONF|FileName=JTAG_Configuration.schdoc|SymbolType=Normal|RawFileName=JTAG_Configuration.schdoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=LVDS_PHY|SchDesignator=LVDS_PHY|FileName=M-LVDS PHY.SchDoc|SymbolType=Normal|RawFileName=M-LVDS PHY.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=PWR_MGT|SchDesignator=PWR_MGT|FileName=POWER_Management.SchDoc|SymbolType=Normal|RawFileName=POWER_Management.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=AMC_FMC_Carrier.SchDoc|Designator=SDRAM|SchDesignator=SDRAM|FileName=SDRAM.SchDoc|SymbolType=Normal|RawFileName=SDRAM.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FHPC1|SchDesignator=FHPC1|FileName=FMC_HPC1.SchDoc|SymbolType=Normal|RawFileName=FMC_HPC1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FHPC2|SchDesignator=FHPC2|FileName=FMC_HPC2.SchDoc|SymbolType=Normal|RawFileName=FMC_HPC2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FMGT|SchDesignator=FMGT|FileName=FPGA_MGT.SchDoc|SymbolType=Normal|RawFileName=FPGA_MGT.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA_SUP|SchDesignator=FPGA_SUP|FileName=FPGA_SUP.SchDoc|SymbolType=Normal|RawFileName=FPGA_SUP.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FSDRAM|SchDesignator=FSDRAM|FileName=FPGA_SDRAM.SchDoc|SymbolType=Normal|RawFileName=FPGA_SDRAM.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=IPMI.SchDoc|Designator=CPU|SchDesignator=CPU|FileName=CPU.SchDoc|SymbolType=Normal|RawFileName=CPU.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=IPMI.SchDoc|Designator=RTCE|SchDesignator=RTCE|FileName=RTCE.SchDoc|SymbolType=Normal|RawFileName=RTCE.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=IPMI.SchDoc|Designator=THERMO|SchDesignator=THERMO|FileName=Thermometers.SchDoc|SymbolType=Normal|RawFileName=Thermometers.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=IPMI.SchDoc|Designator=UUART|SchDesignator=UUART|FileName=USB_UART.SchDoc|SymbolType=Normal|RawFileName=USB_UART.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_10|SchDesignator=SUP_10|FileName=SUP_1V.SchDoc|SymbolType=Normal|RawFileName=SUP_1V.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_12_18|SchDesignator=SUP_12_18|FileName=SUP_1.2_1.8.SchDoc|SymbolType=Normal|RawFileName=SUP_1.2_1.8.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_15|SchDesignator=SUP_15|FileName=SUP_1.5_3.3.SchDoc|SymbolType=Normal|RawFileName=SUP_1.5_3.3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_HPC25|SchDesignator=SUP_HPC25|FileName=SUP_2.5_FMC.SchDoc|SymbolType=Normal|RawFileName=SUP_2.5_FMC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_HPC33|SchDesignator=SUP_HPC33|FileName=SUP_3.3_FMC.SchDoc|SymbolType=Normal|RawFileName=SUP_3.3_FMC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=UI|SchDesignator=UI|FileName=UI_mon.SchDoc|SymbolType=Normal|RawFileName=UI_mon.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Clock_management.SchDoc|Designator=CLK_WR|SchDesignator=CLK_WR|FileName=Clock_WR.SchDoc|SymbolType=Normal|RawFileName=Clock_WR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Clock_management.SchDoc|Designator=FCLK|SchDesignator=FCLK|FileName=FMC_Clocks.SchDoc|SymbolType=Normal|RawFileName=FMC_Clocks.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=TopLevelDocument|FileName=AMC_FMC_Carrier.SchDoc
AMC_ADD=GA0,GA1,GA2
I2C=SCL,SDA
MISC=PRSNT,PG_M2C,PG_C2M
PM_control=1V5_VTT_EN,EN_P1V8,EN_P1V2,EN_FMC1_P12V,EN_FMC2_P12V,EN_FMC1_PVADJ,EN_FMC2_PVADJ,EN_FMC1_P3V3,EN_FMC2_P3V3,DAC_VADJ_CSN,DAC_VADJ_SDI,DAC_VADJ_CLK,DAC_VADJ_RSTN,EN_P1V0,PGOOD_P1V0,EN_P3V3
SCN=ADR0,ADR1,ADR2,ADR3,ADR4,ADR5,ADR6,RSTN
SPI=SCK1,SSEL1,MISO1,MOSI1,PROGRAM_B,DONE,FLASH_Q/D1,FLASH_SI/D0,FPGA_CCLK,FCS_B\
AMC_FABRIC_CLOCK=FCLKA_N,FCLKA_P
AMC_TELECOM_CLOCK=TCLKA_N,TCLKA_P,TCLKB_N,TCLKB_P,TCLKC_N,TCLKC_P,TCLKD_N,TCLKD_P
FPGA_SDRAM_CLK=SDRAM_CLK1_N,SDRAM_CLK1_P,BOOT_CLK_IN
I2C=SDA,SCL
MGT_CLK=PCIE_CLK1_P,PCIE_CLK1_N,PCIE_CLK2_P,PCIE_CLK2_N,FP2_CLK1_P,FP2_CLK1_N,FP2_CLK2_P,FP2_CLK2_N,LINK01_CLK_P,LINK01_CLK_N
PLL_CTRL=VADJ2_SI57X_SDA,VADJ2_SI57X_SCL,PLL_VADJ2_DAC2_SYNC_N,PLL_VADJ2_DAC_SCLK,PLL_VADJ2_DAC1_SYNC_N,PLL_VADJ2_DAC_DIN,VADJ2_SI57X_OE,VADJ2_SI57X_TUNE,VADJ2_CLK_UPDATEN
FMC_CLOCKS=CLK0_M2C_N,CLK0_M2C_P,CLK1_M2C_N,CLK1_M2C_P,CLK2_BIDIR_N,CLK2_BIDIR_P,CLK3_BIDIR_N,CLK3_BIDIR_P,CLK_DIR
FMC_FPGA_CLK_IN=CLK0_M2C_N,CLK0_M2C_P,CLK1_M2C_N,CLK1_M2C_P,CLK2_BIDIR_N,CLK2_BIDIR_P,CLK3_BIDIR_N,CLK3_BIDIR_P
FMC_FPGA_CLK_IN=CLK0_M2C_N,CLK0_M2C_P,CLK1_M2C_N,CLK1_M2C_P,CLK2_BIDIR_N,CLK2_BIDIR_P,CLK3_BIDIR_N,CLK3_BIDIR_P
FMC_J1_HA=HA00_CC_N,HA00_CC_P,HA01_CC_N,HA01_CC_P,HA02_N,HA02_P,HA03_N,HA03_P,HA04_N,HA04_P,HA05_N,HA05_P,HA06_N,HA06_P,HA07_N,HA07_P,HA08_N,HA08_P,HA09_N,HA09_P,HA10_N,HA10_P,HA11_N,HA11_P,HA12_N,HA12_P,HA13_N,HA13_P,HA14_N,HA14_P,HA15_N,HA15_P,HA16_N,HA16_P,HA17_CC_N,HA17_CC_P,HA18_N,HA18_P,HA19_N,HA19_P,HA20_N,HA20_P,HA21_N,HA21_P,HA22_N,HA22_P,HA23_N,HA23_P
FMC_J1_HB=HB00_CC_N,HB00_CC_P,HB01_N,HB01_P,HB02_N,HB02_P,HB03_N,HB03_P,HB04_N,HB04_P,HB05_N,HB05_P,HB06_CC_N,HB06_CC_P,HB07_N,HB07_P,HB08_N,HB08_P,HB09_N,HB09_P,HB10_N,HB10_P,HB11_N,HB11_P,HB12_N,HB12_P,HB13_N,HB13_P,HB14_N,HB14_P,HB15_N,HB15_P,HB16_N,HB16_P,HB17_CC_N,HB17_CC_P,HB18_N,HB18_P,HB19_N,HB19_P,HB20_N,HB20_P,HB21_N,HB21_P
FMC_J1_LA=LA00_CC_N,LA00_CC_P,LA01_CC_N,LA01_CC_P,LA02_N,LA02_P,LA03_N,LA03_P,LA04_N,LA04_P,LA05_N,LA05_P,LA06_N,LA06_P,LA07_N,LA07_P,LA08_N,LA08_P,LA09_N,LA09_P,LA10_N,LA10_P,LA11_N,LA11_P,LA12_N,LA12_P,LA13_N,LA13_P,LA14_N,LA14_P,LA15_N,LA15_P,LA16_N,LA16_P,LA17_CC_N,LA17_CC_P,LA18_CC_N,LA18_CC_P,LA19_N,LA19_P,LA20_N,LA20_P,LA21_N,LA21_P,LA22_N,LA22_P,LA23_N,LA23_P,LA24_N,LA24_P,LA25_N,LA25_P,LA26_N,LA26_P,LA27_N,LA27_P,LA28_N,LA28_P,LA29_N,LA29_P,LA30_N,LA30_P,LA31_N,LA31_P,LA32_N,LA32_P,LA33_N,LA33_P
FMC_J1_VREF=VREF_A_M2C,VREF_B_M2C
I2C=SCL,SDA
FMC_FPGA_CLK_IN=CLK0_M2C_N,CLK0_M2C_P,CLK1_M2C_N,CLK1_M2C_P,CLK2_BIDIR_N,CLK2_BIDIR_P,CLK3_BIDIR_N,CLK3_BIDIR_P
FMC_J1_HA=HA00_CC_N,HA00_CC_P,HA01_CC_N,HA01_CC_P,HA02_N,HA02_P,HA03_N,HA03_P,HA04_N,HA04_P,HA05_N,HA05_P,HA06_N,HA06_P,HA07_N,HA07_P,HA08_N,HA08_P,HA09_N,HA09_P,HA10_N,HA10_P,HA11_N,HA11_P,HA12_N,HA12_P,HA13_N,HA13_P,HA14_N,HA14_P,HA15_N,HA15_P,HA16_N,HA16_P,HA17_CC_N,HA17_CC_P,HA18_N,HA18_P,HA19_N,HA19_P,HA20_N,HA20_P,HA21_N,HA21_P,HA22_N,HA22_P,HA23_N,HA23_P
FMC_J1_HB=HB00_CC_N,HB00_CC_P,HB01_N,HB01_P,HB02_N,HB02_P,HB03_N,HB03_P,HB04_N,HB04_P,HB05_N,HB05_P,HB06_CC_N,HB06_CC_P,HB07_N,HB07_P,HB08_N,HB08_P,HB09_N,HB09_P,HB10_N,HB10_P,HB11_N,HB11_P,HB12_N,HB12_P,HB13_N,HB13_P,HB14_N,HB14_P,HB15_N,HB15_P,HB16_N,HB16_P,HB17_CC_N,HB17_CC_P,HB18_N,HB18_P,HB19_N,HB19_P,HB20_N,HB20_P,HB21_N,HB21_P
FMC_J1_LA=LA00_CC_N,LA00_CC_P,LA01_CC_N,LA01_CC_P,LA02_N,LA02_P,LA03_N,LA03_P,LA04_N,LA04_P,LA05_N,LA05_P,LA06_N,LA06_P,LA07_N,LA07_P,LA08_N,LA08_P,LA09_N,LA09_P,LA10_N,LA10_P,LA11_N,LA11_P,LA12_N,LA12_P,LA13_N,LA13_P,LA14_N,LA14_P,LA15_N,LA15_P,LA16_N,LA16_P,LA17_CC_N,LA17_CC_P,LA18_CC_N,LA18_CC_P,LA19_N,LA19_P,LA20_N,LA20_P,LA21_N,LA21_P,LA22_N,LA22_P,LA23_N,LA23_P,LA24_N,LA24_P,LA25_N,LA25_P,LA26_N,LA26_P,LA27_N,LA27_P,LA28_N,LA28_P,LA29_N,LA29_P,LA30_N,LA30_P,LA31_N,LA31_P,LA32_N,LA32_P,LA33_N,LA33_P
FMC_J1_VREF=VREF_A_M2C,VREF_B_M2C
FPGA_FLASH=FLASH_FCS_B\,FLASH_D3,FLASH_D2,FLASH_Q/D1,FLASH_SI/D0
PLL_CTRL=VADJ2_SI57X_SDA,VADJ2_SI57X_SCL,PLL_VADJ2_DAC2_SYNC_N,PLL_VADJ2_DAC_SCLK,PLL_VADJ2_DAC1_SYNC_N,PLL_VADJ2_DAC_DIN,VADJ2_SI57X_OE,VADJ2_SI57X_TUNE,VADJ2_CLK_UPDATEN
FMC_CLOCKS=CLK_DIR,CLK0_M2C_N,CLK0_M2C_P,CLK1_M2C_N,CLK1_M2C_P,CLK2_BIDIR_N,CLK2_BIDIR_P,CLK3_BIDIR_N,CLK3_BIDIR_P
FMC_J1_DP=DP0_C2M_N,DP0_C2M_P,DP1_C2M_N,DP1_C2M_P,DP2_C2M_N,DP2_C2M_P,DP3_C2M_N,DP3_C2M_P,DP0_M2C_N,DP0_M2C_P,DP1_M2C_N,DP1_M2C_P,DP2_M2C_N,DP2_M2C_P,DP3_M2C_N,DP3_M2C_P
FMC_J1_HA=HA00_CC_N,HA00_CC_P,HA01_CC_N,HA01_CC_P,HA02_N,HA02_P,HA03_N,HA03_P,HA04_N,HA04_P,HA05_N,HA05_P,HA06_N,HA06_P,HA07_N,HA07_P,HA08_N,HA08_P,HA09_N,HA09_P,HA10_N,HA10_P,HA11_N,HA11_P,HA12_N,HA12_P,HA13_N,HA13_P,HA14_N,HA14_P,HA15_N,HA15_P,HA16_N,HA16_P,HA17_CC_N,HA17_CC_P,HA18_N,HA18_P,HA19_N,HA19_P,HA20_N,HA20_P,HA21_N,HA21_P,HA22_N,HA22_P,HA23_N,HA23_P
FMC_J1_HB=HB00_CC_N,HB00_CC_P,HB01_N,HB01_P,HB02_N,HB02_P,HB03_N,HB03_P,HB04_N,HB04_P,HB05_N,HB05_P,HB06_CC_N,HB06_CC_P,HB07_N,HB07_P,HB08_N,HB08_P,HB09_N,HB09_P,HB10_N,HB10_P,HB11_N,HB11_P,HB12_N,HB12_P,HB13_N,HB13_P,HB14_N,HB14_P,HB15_N,HB15_P,HB16_N,HB16_P,HB17_CC_N,HB17_CC_P,HB18_N,HB18_P,HB19_N,HB19_P,HB20_N,HB20_P,HB21_N,HB21_P
FMC_J1_JTAG=TCK,TDI,TDO,TMS,TRST_L
FMC_J1_LA=LA00_CC_N,LA00_CC_P,LA01_CC_N,LA01_CC_P,LA02_N,LA02_P,LA03_N,LA03_P,LA04_N,LA04_P,LA05_N,LA05_P,LA06_N,LA06_P,LA07_N,LA07_P,LA08_N,LA08_P,LA09_N,LA09_P,LA10_N,LA10_P,LA11_N,LA11_P,LA12_N,LA12_P,LA13_N,LA13_P,LA14_N,LA14_P,LA15_N,LA15_P,LA16_N,LA16_P,LA17_CC_N,LA17_CC_P,LA18_CC_N,LA18_CC_P,LA19_N,LA19_P,LA20_N,LA20_P,LA21_N,LA21_P,LA22_N,LA22_P,LA23_N,LA23_P,LA24_N,LA24_P,LA25_N,LA25_P,LA26_N,LA26_P,LA27_N,LA27_P,LA28_N,LA28_P,LA29_N,LA29_P,LA30_N,LA30_P,LA31_N,LA31_P,LA32_N,LA32_P,LA33_N,LA33_P
FMC_J1_POWER=3P3VAUX,12P0V,VIO_B_M2C
FMC_J1_VREF=VREF_A_M2C,VREF_B_M2C
GBT_CLOCK=GBTCLK0_M2C_N,GBTCLK0_M2C_P,GBTCLK1_M2C_N,GBTCLK1_M2C_P
I2C=SCL,SDA
MISC=PRSNT,PG_M2C,PG_C2M
FMC_J1_JTAG=TCK,TDI,TDO,TMS,TRST_L
FPGA_FLASH=FLASH_SI/D0,FLASH_Q/D1,FLASH_D2,FLASH_D3,FLASH_FCS_B\
FPGA_THERM=DXN,DXP
SPI=SCK1,SSEL1,MISO1,MOSI1,PROGRAM_B,DONE,FLASH_Q/D1,FLASH_SI/D0,FPGA_CCLK,FCS_B\
FAT_PIPE1=RX4_P,RX4_N,TX4_N,TX4_P,RX5_P,RX5_N,TX5_N,TX5_P,RX6_P,RX6_N,TX6_N,TX6_P,RX7_P,RX7_N,TX7_N,TX7_P
FAT_PIPE2=RX8_P,RX8_N,TX8_N,TX8_P,RX9_P,RX9_N,TX9_N,TX9_P,RX10_P,RX10_N,TX10_N,TX10_P,RX11_P,RX11_N,TX11_N,TX11_P
FMC_J1_DP=DP0_C2M_N,DP0_C2M_P,DP1_C2M_N,DP1_C2M_P,DP2_C2M_N,DP2_C2M_P,DP3_C2M_N,DP3_C2M_P,DP0_M2C_N,DP0_M2C_P,DP1_M2C_N,DP1_M2C_P,DP2_M2C_N,DP2_M2C_P,DP3_M2C_N,DP3_M2C_P
GBT_CLOCK=GBTCLK0_M2C_N,GBTCLK0_M2C_P,GBTCLK1_M2C_N,GBTCLK1_M2C_P
MGT_CLK=PCIE_CLK1_P,PCIE_CLK1_N,PCIE_CLK2_P,PCIE_CLK2_N,FP2_CLK1_P,FP2_CLK1_N,FP2_CLK2_P,FP2_CLK2_N,LINK01_CLK_P,LINK01_CLK_N
PORT0=RX0_P,RX0_N,TX0_N,TX0_P
PORT1=RX1_P,RX1_N,TX1_N,TX1_P
PORT2=RX2_P,RX2_N,TX2_N,TX2_P
PORT3=RX3_P,RX3_N,TX3_N,TX3_P
DDR=DQS0_P,DQS0_N,DQS1_P,DQS1_N,DQS2_P,DQS2_N,DQS3_P,DQS3_N,CLK0_N,CLK0_P,RST_N,ODT0,CE0_N,BA0,BA1,BA2,A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,CAS_N,RAS_N,WE_N,CKE0,DQM0,D0,D1,D2,D3,D4,D5,D6,D7,DQM1,D8,D9,D10,D11,D12,D13,D14,D15,DQM2,D16,D17,D18,D19,D20,D21,D22,D23,DQM3,D24,D25,D26,D27,D28,D29,D30,D31
FPGA_SDRAM_CLK=SDRAM_CLK1_N,SDRAM_CLK1_P,BOOT_CLK_IN,SDRAM_CLK2_N
MLVDS-FPGA=IO_TX_P17,IO_TX_P18,IO_TX_P19,IO_TX_P20,IO_RX_P17,IO_RX_P18,IO_RX_P19,IO_RX_P20,R\E\_DE_TX_P17,R\E\_DE_TX_P18,R\E\_DE_TX_P19,R\E\_DE_TX_P20,R\E\_DE_RX_P17,R\E\_DE_RX_P18,R\E\_DE_RX_P19,R\E\_DE_RX_P20
AMC_JTAG=TRST#,TMS,TDO,TDI,TCK
FMC_J1_JTAG=TCK,TDI,TDO,TMS,TRST_L
SCN=ADR0,ADR1,ADR2,ADR3,ADR4,ADR5,ADR6,RSTN
MLVDS=RX17_P,RX17_N,TX17_N,TX17_P,RX18_P,RX18_N,TX18_N,TX18_P,RX19_P,RX19_N,TX19_N,TX19_P,RX20_P,RX20_N,TX20_N,TX20_P
MLVDS-FPGA=IO_TX_P17,IO_TX_P18,IO_TX_P19,IO_TX_P20,IO_RX_P17,IO_RX_P18,IO_RX_P19,IO_RX_P20,R\E\_DE_TX_P17,R\E\_DE_TX_P18,R\E\_DE_TX_P19,R\E\_DE_TX_P20,R\E\_DE_RX_P17,R\E\_DE_RX_P18,R\E\_DE_RX_P19,R\E\_DE_RX_P20
FMC_J1_POWER=3P3VAUX,12P0V,VIO_B_M2C
PM_control=1V5_VTT_EN,EN_P1V8,EN_P1V2,EN_FMC1_P12V,EN_FMC2_P12V,EN_FMC1_PVADJ,EN_FMC2_PVADJ,EN_FMC1_P3V3,EN_FMC2_P3V3,DAC_VADJ_CSN,DAC_VADJ_SDI,DAC_VADJ_CLK,DAC_VADJ_RSTN,EN_P1V0,PGOOD_P1V0,EN_P3V3
DDR=DQM0,DQM1,DQM2,DQM3,DQS0_P,DQS0_N,DQS1_P,DQS1_N,DQS2_P,DQS2_N,DQS3_P,DQS3_N,CE0_N,BA0,BA1,BA2,A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,CAS_N,RAS_N,WE_N,CKE0,D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15,D16,D17,D18,D19,D20,D21,D22,D23,D24,D25,D26,D27,D28,D29,D30,D31,ODT0,RST_N,CLK0_N,CLK0_P
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.