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Commit f298b2b7 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Add a micropipeline demo for iCEstick

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demo/hardware/Makefile 0 → 100644
View file @ f298b2b7
SYN = yosys
PNR = nextpnr-ice40
GEN = icepack
PROG = iceprog
TOP = micropipeline.v
PCF = icestick.pcf
DEVICE = 1k
OUTPUT = $(patsubst %.v,%.bin,$(TOP))
all: $(OUTPUT)
%.bin: %.asc
$(GEN) $< $@
%.asc: %.json
$(PNR) --hx1k --pcf $(PCF) --asc $@ --json $<
%.json: %.v
$(SYN) -p "read_verilog $<; synth_ice40 -flatten -json $@"
clean:
rm -f *.bin *.json *.asc
flash: $(OUTPUT)
$(PROG) $<
.PHONY: all clean flash
demo/hardware/icestick.pcf 0 → 100644
View file @ f298b2b7
# Generic iCEstick placement constraints file
# Red LEDs
set_io LED0 99
set_io LED1 98
set_io LED2 97
set_io LED3 96
# Green LED
set_io LED4 95
# FTDI Port B UART
#set_io DCDn 1
#set_io DSRn 2
#set_io DTRn 3
#set_io CTSn 4
#set_io RTSn 7
set_io RS232_Tx_TTL 8
set_io RS232_Rx_TTL 9
# 12 MHz clock
set_io iCE_CLK 21
demo/hardware/micropipeline.v 0 → 100644
View file @ f298b2b7
`include "../../ip_cores/osdvu/uart.v"
`include "../../hdl/verilog/asyncart_demo.v"
module top(
input iCE_CLK,
input RS232_Rx_TTL,
output RS232_Tx_TTL,
output LED0,
output LED1,
output LED2,
output LED3,
output LED4
);
wire reset = 0;
wire enable = 1;
wire received;
reg fetched;
wire [7:0] rx_byte;
wire is_receiving;
wire is_transmitting;
wire recv_error;
parameter PIPE_DEPTH = 3;
wire [31:0] data_micropipeline;
reg act, rst;
uart #(
.baud_rate(115200), // The baud rate in kilobits/s
.sys_clk_freq(12000000) // The master clock frequency
)
uart0(
.clk(iCE_CLK), // The master clock for this module
.rst(reset), // Synchronous reset
.rx(RS232_Rx_TTL), // Incoming serial line
.tx(RS232_Tx_TTL), // Outgoing serial line
.transmit(transmit), // Signal to transmit
.tx_byte(tx_byte), // Byte to transmit
.received(received), // Indicated that a byte has been received
.rx_byte(rx_byte), // Byte received
.is_receiving(is_receiving), // Low when receive line is idle
.is_transmitting(is_transmitting),// Low when transmit line is idle
.recv_error(recv_error) // Indicates error in receiving packet.
);
always @(posedge iCE_CLK) begin
if (received) begin
act <= rx_byte[1];
rst <= rx_byte[0];
end
end
asyncart_demo asyncart_demo_instance (
.act_in(act),
.rst_in(rst),
.data_out(data_micropipeline)
);
// Connect the Red LEDs to the 4 MSB bits in the sink registed (last pipeline stage)
assign {LED3, LED2, LED1, LED0} = data_micropipeline[31:28];
assign LED4 = act;
endmodule
ip_cores/osdvu/CHANGELOG 0 → 100644
View file @ f298b2b7
Aaron Dahlen 11 Apr 13:
1) added TX_RECOVER state that waits for "transmit" to be
released. This prevents the transmission of multiple characters
for systems with a slowly changing transmit line.
2) Tested on Digilent NEXYS3 FPGA at 921600 baud (55 slices consumed).
Also tested at 300 baud (76 slices). Not that the lower baud rate
consumes additional FPGA fabric since the clock dividers are larger.
3) Problems with error at high baud rates. Split each bit into
8 sections. Discarded the first three section and sampled the last 5.
poor results.
4) Continued the high bit error problem by eliminating the
clock_divide prescaler. Success! the system now operated
error free at 91600 baud. For this test a Digilent NEXYS3
board with a 100 MHz clock was used.
The solution was to implement rx_clk and tx_clk. These
counters directly count down the ticks of the high speed
system clock.
On the downside the complexity of the design has risen as
has the required fabric. The module configured for 300 baud
now consumes 111 Macrocells in a coolrunner II. It consumes
79 slices in the Spartan 6.
Aaron Dahlen, 10 Apr 13:
1) Continued work on eliminating warnings. It seems that
the synthesis for a Spartan-6 is different that the
Spartan-3 and coolrunner. Unable to clear warnings for both.
This code synthesizes without warning for Coolrunner and Spartan 3.
2) Size in CoolrunnerII is 68 to 89 macrocells. Actual size is
baud rate dependent with higher rates consuming less FPGA fabric.
3) removed recv_state and tx_state from the module output
Aaron Dahlen, 07 Apr 13:
1) Accepts baud_rate and clock_rate as parameters. Auto calculates
clock_divide.
2) Now uses localparam to prevent parameter modification.
3) Partially developed test bench, added hooks to see internal operation.
These should probable be removed in the future...
4) Eliminated warnings from the XILINX ISE 14.4 synthesizer
ip_cores/osdvu/LICENCE 0 → 100644
View file @ f298b2b7
The MIT License
Copyright (c) 2010 Timothy Goddard
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
\ No newline at end of file
ip_cores/osdvu/README 0 → 100644
View file @ f298b2b7
Open Source Documented Verilog UART
Published under the terms of the MIT licence. See LICENCE for licensing information.
== Purpose ==
This module was created as a result of my own need for a UART (serial line I/O) component and frustration at the difficulty of integrating the existing available components in to my own project. All the open source UART modules I found were either difficult to interface with, usually due to being more clever than I wanted them to be and had poor documentation for their interfaces. They were also generally written in VHDL, which since I've never written VHDL made it a little difficult to read to work out the interfacing issues for myself. The frustration of finding such a simple component so hard to use prompted the decision to create my own, and document it for beginners like myself.
I hope that this module will be documented to a better standard than most I've come across. Please send me email at tim@goddard.net.nz if you have trouble understanding it. Improvements are also welcome.
== What would I use this for? ==
A UART is a useful component for controlling asynchronous (without a separate clock line) serial buses. It can be used via a level converter to talk to the RS232 serial port of a computer. This is not, however, the only application. It could also be used as a local chip bus, or with differential signalling to connect to peripherals over quite long distances.
== I/O Standards, Compatability ==
This follows standard UART signalling methods with the following properties:
* Expects to send and receive data as 8 data bits, no parity bits.
* Default baud rate is 9600 with a 50MHz clock. This is configurable.
* Samples values roughly in the middle of each bit (may drift slightly).
* Sends and receives least significant bit first.
* Expects to receive at least 1 stop bit. Will not check for more, but won't fail either.
* Transmits 2 stop bits.
== Usage ==
The UART component can be included in your application like this:
uart MyInstanceName (clk, rst, rx, tx, transmit, tx_byte, received, rx_byte, is_receiving, is_transmitting, recv_error);
These are the lines and what they each need to be connected to:
* "clk" is the master clock for this component.
By default this will run at 9600 baud with a clock of 50MHz, but this can be altered as described in the "Adjusting Clock Rate / Baud Rate" section below.
* "rst" is a synchronous reset line (resets if high when the rising edge of clk arrives).
Raising this high for one cycle of clk will interrupt any transmissions in progress and set it back to an idle state. Doing this unneccessarily is not recommended - the receive component could become confused if reset halfway through a transmission. This can be unconnected if you don't need to reset the component.
* "rx" is the serial line which the component will receive data on.
This would usually be connected to an outside pin.
* "tx" is the serial line which the component will transmit data on.
This would usually be connected to an outside pin.
* The input flag "transmit" is a signal you use to indicate that the UART should start a transmission.
If the transmit line is idle and this is raised for one clock cycle, the component will copy the content of the tx_byte input and start transmitting it. If raised while the line is busy, this signal will be ignored. The is_transmitting output mentioned later can be used to test this and avoid missing a byte.
* The input "tx_byte" is an 8-bit bus containing the byte to be transmitted when "transmit" is raised high.
When "transmit" is low, this may change without interrupting the transfer.
* "received" is an output flag which is raised high for one cycle of clk when a byte is received.
* The output "rx_data" is set to the value of the byte which has just been received when "received" is raised.
It is recommended that this be used immediately in the cycle when "raised" is high or saved in to a register for future use. While this is likely to remain accurate until the start of the next incoming byte arrives, this should not be relied on.
* The output "is_receiving" indicates that we are currently receiving data on the rx line.
This could be used for example to provide an early warning that a byte may be about to be received. When this signal is true, it will not become false again until either "received" or "recv_error" has been asserted. If you don't need early warning, this can safely be left disconnected.
* The output "is_transmitting" indicates that we are currently sending data on the tx line.
This is often important to track, because we can only send one byte at once. If we need to send another byte and this is high, the code outside will have to wait until this goes low before it can begin. This can be ignored if you know that you will never try to transmit while another transmission is in progress, for example when transmissions happen at fixed intervals longer than the time it takes to transmit a packet (11 bit periods - just under 1.2ms at 9600 baud) .
* recv_error is an output indicating that a malformed or incomplete byte was received.
If you simply wish to ignore bad incoming bytes, you can safely leave this signal disconnected.
With "rst", "is_receiving" and "recv_error" disconnected, the invocation would look like:
uart MyInstanceName (clk, , rx, tx, transmit, tx_byte, received, rx_byte, , is_transmitting, );
== Adjusting Clock Rate / Baud Rate ==
The clock rate and baud rate can be altered by changing the CLOCK_DIVIDE parameter passed in to the uart module. This value is calculated by taking the clock frequency in Hz (for example, 50MHz is 50,000,000 Hz), dividing it by the baud rate times 4 (for example 9600)
CLOCK_DIVIDE = Frequency(clk) / (4 * Baud)
In the example given, the resulting constant is 50000000 / (4 * 9600) = 1302 . This is the value that the module has by default. To create a UART running at a different rate, insert the CLOCK_DIVIDE value in to the initialisation like:
uart #(.CLOCK_DIVIDE( 1302 )) MyInstanceName (clk, ...);
ip_cores/osdvu/tb_uart.v 0 → 100644
View file @ f298b2b7
`timescale 1ns / 1ps
//*************************************************************
//
// Module: tb_uart
//
//** Description **********************************************
//
// Test bench for uart module.
//
//** HISTORY **************************************************
//
// 07 Apr 13: initial design and test
//
// 11 Apr 13: clean up...
//
//*************************************************************
module tb_uart;
/* Test bench specific parameters */
localparam baud_rate = 19200;
localparam sys_clk_freq = 100000000;
/* Clock simulation */
localparam clock_tick = 10; // in nanoseconds
/* General shortcuts */
localparam T = 1'b1;
localparam F = 1'b0;
//** SIGNAL DECLARATIONS **************************************
/* UUT signals */
reg clk;
reg reset;
reg rx;
wire tx;
reg transmit;
reg [7:0]tx_byte;
wire received;
wire [7:0] rx_byte;
wire is_receiving;
wire is_transmitting;
wire recv_error;
wire [3:0] rx_samples;
wire [3:0]rx_sample_countdown;
// reg i;
reg[7:0] cnt;
reg[7:0] rcv_reg;
//** INSTANTIATE THE UNIT UNDER TEST(UUT)**********************
uart
#(.baud_rate(baud_rate),
.sys_clk_freq(sys_clk_freq)
)
uart(
.clk(clk),
.rst(reset),
.rx(rx),
.tx(tx),
.transmit(transmit),
.tx_byte(tx_byte),
.received(received),
.rx_byte(rx_byte),
.is_receiving(is_receiving),
.is_transmitting(is_transmitting),
.recv_error(recv_error),
.rx_samples(rx_samples),
.rx_sample_countdown(rx_sample_countdown)
);
//** Clock ****************************************************
always begin
clk = T;
#(clock_tick/2);
clk = F;
#(clock_tick/2);
end
//** UUT Tests ************************************************
initial begin
initial_conditions();
reset_UUT();
test_rcvr(8'h55);
test_rcvr(8'hAA);
test_rcvr(8'h45);
xmit_char(8'hAA); // should transmit one byte
wait_while_transmitting;
transmit = T; // character should be transmitted once
delay((1e8/baud_rate) * 10 * 2);
transmit = F;
xmit_char(8'h55); // transmit one byte
wait_while_transmitting;
//FIX ME - add tests for receive functions...
$finish;
end
// The testbench receiver is constantly running...
always begin
// while (tx == T)begin
// @(posedge clk);
// rcv_reg = 0;
// end
wait(!tx);
rcv_reg = 0;
delay(1e8/baud_rate); // delay for start bit
for(cnt = 0; cnt<8; cnt = cnt + 1) begin
delay((1e8/baud_rate) / 2);
rcv_reg = {tx, rcv_reg[7:1]};
delay((1e8/baud_rate) / 2);
end
// delay((1e8/baud_rate)/2); // delay fro stop bit
wait(tx);
end
//** Tasks ****************************************************
task initial_conditions(); begin
repeat(5) @(posedge clk)
reset = F;
transmit = F;
end endtask
task reset_UUT(); begin
@(posedge clk)
reset = T;
@(posedge clk)
reset = F;
end endtask
task delay(input integer N); begin
repeat(N) @(posedge clk);
end endtask
task xmit_char(input integer C); begin
tx_byte = C;
@(posedge clk)
transmit = T;
@(posedge clk)
transmit = F;
end endtask
task wait_while_transmitting; begin
@(negedge is_transmitting);
repeat(10) @(posedge clk);
end endtask
task test_rcvr (input reg[7:0] C);
integer i;
reg [7:0] shift_reg;
begin
shift_reg = C;
@(posedge clk)
rx = F; // send start bit
delay(1e8/baud_rate);
for(i = 0; i<8; i = i + 1) begin // send serial data LSB first
rx = shift_reg[0];
shift_reg = shift_reg >> 1;
delay(1e8/baud_rate);
end
rx = T; // send stop bit
delay(1e8/baud_rate);
if(C == rx_byte)begin
$display("rcvr test pass");
end else begin
$display("rcvr test fail %d not equal %d", C, rx_byte);
end
end endtask
endmodule
ip_cores/osdvu/uart.v 0 → 100644
View file @ f298b2b7
`timescale 1ns / 1ps
// Documented Verilog UART
// Copyright (C) 2010 Timothy Goddard (tim@goddard.net.nz)
// 2013 Aaron Dahlen
// Distributed under the MIT licence.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
//** INSTANTIATION ********************************************
//
// To instantiate this module copy this section to your main code...
//
// uart #(
// .baud_rate(baud_rate), // default is 9600
// .sys_clk_freq(sys_clk_freq) // default is 100000000
// )
// instance_name(
// .clk(clk), // The master clock for this module
// .rst(rst), // Synchronous reset
// .rx(rx), // Incoming serial line
// .tx(tx), // Outgoing serial line
// .transmit(transmit), // Signal to transmit
// .tx_byte(tx_byte), // Byte to transmit
// .received(received), // Indicated that a byte has been received
// .rx_byte(rx_byte), // Byte received
// .is_receiving(is_receiving), // Low when receive line is idle
// .is_transmitting(is_transmitting),// Low when transmit line is idle
// .recv_error(recv_error) // Indicates error in receiving packet.
// //.recv_state(recv_state), // for test bench
// //.tx_state(tx_state) // for test bench
// );
//
module uart(
input clk, // The master clock for this module
input rst, // Synchronous reset
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Assert to begin transmission
input [7:0] tx_byte, // Byte to transmit
output received, // Indicates that a byte has been received
output [7:0] rx_byte, // Byte received
output wire is_receiving, // Low when receive line is idle.
output wire is_transmitting,// Low when transmit line is idle.
output wire recv_error, // Indicates error in receiving packet.
output reg [3:0] rx_samples,
output reg [3:0] rx_sample_countdown
);
// The clock_divider is calculated using baud_rate and sys_clk_freq.
// To modify baud rate you can modify the defaults shown below or instantiate
// the module using the template shown in the INSTANTIATION section above.
// For aditional information about instantiation please see:
// http://www.sunburst-design.com/papers/CummingsHDLCON2002_Parameters_rev1_2.pdf
parameter baud_rate = 9600;
parameter sys_clk_freq = 100000000;
localparam one_baud_cnt = sys_clk_freq / (baud_rate);
//** SYMBOLIC STATE DECLARATIONS ******************************
localparam [2:0]
RX_IDLE = 3'd0,
RX_CHECK_START = 3'd1,
RX_SAMPLE_BITS = 3'd2,
RX_READ_BITS = 3'd3,
RX_CHECK_STOP = 3'd4,
RX_DELAY_RESTART = 3'd5,
RX_ERROR = 3'd6,
RX_RECEIVED = 3'd7;
localparam [1:0]
TX_IDLE = 2'd0,
TX_SENDING = 2'd1,
TX_DELAY_RESTART = 2'd2,
TX_RECOVER = 2'd3;
//** SIGNAL DECLARATIONS **************************************
reg [log2(one_baud_cnt * 16)-1:0] rx_clk;
reg [log2(one_baud_cnt)-1:0] tx_clk;
reg [2:0] recv_state = RX_IDLE;
reg [3:0] rx_bits_remaining;
reg [7:0] rx_data;
reg tx_out = 1'b1;
reg [1:0] tx_state = TX_IDLE;
reg [3:0] tx_bits_remaining;
reg [7:0] tx_data;
//** ASSIGN STATEMENTS ****************************************
assign received = recv_state == RX_RECEIVED;
assign recv_error = recv_state == RX_ERROR;
assign is_receiving = recv_state != RX_IDLE;
assign rx_byte = rx_data;
assign tx = tx_out;
assign is_transmitting = tx_state != TX_IDLE;
//** TASKS / FUNCTIONS ****************************************
function integer log2(input integer M);
integer i;
begin
log2 = 1;
for (i = 0; 2**i <= M; i = i + 1)
log2 = i + 1;
end endfunction
//** Body *****************************************************
always @(posedge clk) begin
if (rst) begin
recv_state = RX_IDLE;
tx_state = TX_IDLE;
end
// Countdown timers for the receiving and transmitting
// state machines are decremented.
if(rx_clk) begin
rx_clk = rx_clk - 1'd1;
end
if(tx_clk) begin
tx_clk = tx_clk - 1'd1;
end
//** Receive state machine ************************************
case (recv_state)
RX_IDLE: begin
// A low pulse on the receive line indicates the
// start of data.
if (!rx) begin
// Wait 1/2 of the bit period
rx_clk = one_baud_cnt / 2;
recv_state = RX_CHECK_START;
end
end
RX_CHECK_START: begin
if (!rx_clk) begin
// Check the pulse is still there
if (!rx) begin
// Pulse still there - good
// Wait the bit period plus 3/8 of the next
rx_clk = (one_baud_cnt / 2) + (one_baud_cnt * 3) / 8;
rx_bits_remaining = 8;
recv_state = RX_SAMPLE_BITS;
rx_samples = 0;
rx_sample_countdown = 5;
end else begin
// Pulse lasted less than half the period -
// not a valid transmission.
recv_state = RX_ERROR;
end
end
end
RX_SAMPLE_BITS: begin
// sample the rx line multiple times
if (!rx_clk) begin
if (rx) begin
rx_samples = rx_samples + 1'd1;
end
rx_clk = one_baud_cnt / 8;
rx_sample_countdown = rx_sample_countdown -1'd1;
recv_state = rx_sample_countdown ? RX_SAMPLE_BITS : RX_READ_BITS;
end
end
RX_READ_BITS: begin
if (!rx_clk) begin
// Should be finished sampling the pulse here.
// Update and prep for next
if (rx_samples > 3) begin
rx_data = {1'd1, rx_data[7:1]};
end else begin
rx_data = {1'd0, rx_data[7:1]};
end
rx_clk = (one_baud_cnt * 3) / 8;
rx_samples = 0;
rx_sample_countdown = 5;
rx_bits_remaining = rx_bits_remaining - 1'd1;
if(rx_bits_remaining)begin
recv_state = RX_SAMPLE_BITS;
end else begin
recv_state = RX_CHECK_STOP;
rx_clk = one_baud_cnt / 2;
end
end
end
RX_CHECK_STOP: begin
if (!rx_clk) begin
// Should resume half-way through the stop bit
// This should be high - if not, reject the
// transmission and signal an error.
recv_state = rx ? RX_RECEIVED : RX_ERROR;
end
end
RX_ERROR: begin
// There was an error receiving.
// Raises the recv_error flag for one clock
// cycle while in this state and then waits
// 2 bit periods before accepting another
// transmission.
rx_clk = 8 * sys_clk_freq / (baud_rate);
recv_state = RX_DELAY_RESTART;
end
// why is this state needed? Why not go to idle and wait for next?
RX_DELAY_RESTART: begin
// Waits a set number of cycles before accepting
// another transmission.
recv_state = rx_clk ? RX_DELAY_RESTART : RX_IDLE;
end
RX_RECEIVED: begin
// Successfully received a byte.
// Raises the received flag for one clock
// cycle while in this state.
recv_state = RX_IDLE;
end
endcase
//** Transmit state machine ***********************************
case (tx_state)
TX_IDLE: begin
if (transmit) begin
// If the transmit flag is raised in the idle
// state, start transmitting the current content
// of the tx_byte input.
tx_data = tx_byte;
// Send the initial, low pulse of 1 bit period
// to signal the start, followed by the data
// tx_clk_divider = clock_divide;
tx_clk = one_baud_cnt;
tx_out = 0;
tx_bits_remaining = 8;
tx_state = TX_SENDING;
end
end
TX_SENDING: begin
if (!tx_clk) begin
if (tx_bits_remaining) begin
tx_bits_remaining = tx_bits_remaining - 1'd1;
tx_out = tx_data[0];
tx_data = {1'b0, tx_data[7:1]};
tx_clk = one_baud_cnt;
tx_state = TX_SENDING;
end else begin
// Set delay to send out 2 stop bits.
tx_out = 1;
tx_clk = 16 * one_baud_cnt;// tx_countdown = 16;
tx_state = TX_DELAY_RESTART;
end
end
end
TX_DELAY_RESTART: begin
// Wait until tx_countdown reaches the end before
// we send another transmission. This covers the
// "stop bit" delay.
tx_state = tx_clk ? TX_DELAY_RESTART : TX_RECOVER;// TX_IDLE;
end
TX_RECOVER: begin
// Wait unitil the transmit line is deactivated. This prevents repeated characters
tx_state = transmit ? TX_RECOVER : TX_IDLE;
end
endcase
end
endmodule
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