The AsyncArt Project is comprised by a set of Open-Source HDL libraries and examples
targeted to the efficient implementation of Globally Asynchronous, Locally Synchronous (GALS)
design architectures over Commercial-Off-The-Shelf FPGA devices.
More than a standard library, the core of the
AsyncArt project is a collection of very simple reference design
examples that contain useful tricks and methodologies that can be easily
extended to more complex projects.
A GALS circuit consists of a set of locally synchronous modules communicating with each other via asynchronous wrappers. In this way, each synchronous subsystem ("clock domain") can run on its own locally generated independent clock (frequency), while sharing data with their neighboring modules by using asynchronous micropipelines.
One of the critical advantages of GALS over pure synchronous designs is the much lower electromagnetic interference (EMI). The CMOS circuit (logic gates) requires relatively large supply current when changing state from 0 to 1. These changes are aggregated for synchronous circuit as most changes are initialized by an active clock edge. Therefore, large spikes on supply current occur at active clock edges in synchronous designs. These spikes can cause large electromagnetic conducted and radiated interference, and may ultimately lead to circuit malfunction. In order to limit these spikes large number of decoupling capacitors are used, but this is not always possible and no more than hack for the actual problem.
Another solution is to use a GALS design style: there are different (e.g. phase shifted, rising and falling active edge) clock signal regimes thus supply current spikes do not aggregate at the same time. Consequently, GALS design style is often used in System-on-Chip (SoC) devices, being of special interest for Network-on-Chip (NoC) based architectures.
The original AsyncArt research project was conducted by Javier Garcia-Lasheras between 2005 and 2007 with the support of the Communication, Signal and Microwaves group of the Public University of Navarre. The target for this research was to demonstrate the advantages of a full featured System-on-Chip ASIC implemented with the GALS approach. After heavy testing in FPGAs, an ASIC chip dubbed PNX-2006 was successfully built, demonstrating Asynchronous Network-on-Chip capabilities and active power consumption and EM interference reduction techniques.
During the research, we noticed that the FPGA prototypes performed very close to the physical limit of the technology while incurring in a very low logic overhead. Indeed, they performed far better than the PNX-2006, because while the foundry we used for the ASIC was based on 0.5 micrometer CMOS process, the FPGA devices for the prototypes were based on 45 and 90 nanometers processes. In order to allow further research on this topic, we published the internal technical details for our GALS implementation for FPGAs in the following paper:
Five years later, in 2012, the original FPGA projects that served as prototypes for the PNX-2006 ASIC chip were published as free/open source in the Open Hardware Repository. Those designs were implemented over Xilinx 3th and 4th Series devices, so they were updated to Xilinx 6th Series devices and distributed as a collection of schematic projects for Xilinx ISE:
As a companion for this project collection, an AsyncArt Quick-Start was originally published as a blog series on
All Programmable Planet in 2013, an online
community sponsored by Xilinx. After this community was closed, the blog
series was republished in the EETimes in 2014:
Here we see a suite of circuits that demonstrate different
aspects of asynchronous micropipelines.
In order to allow for a widespread testing and potential adoption of the technology by community, we first worked in migrating the reference designs to FPGA devices from other vendors. In this way, we verified that the asynchronous logic circuitry in the AsyncArt GALS approach works on devices from Xilinx, Intel (formerly Altera), Microsemi (formerly Actel) and Lattice.
In all of the cases, the main of the problems at the time of applying the GALS approach to complex SoC designs are related with the obscurity and lack of the required fine-grained control in the proprietary FPGA toolchains. When dealing with GALS, you need to check different critical paths and clock constraints for several design regions, and this is not always possible with proprietary tools.
For this reason, we are currently migrating the designs to a 100% FLOSS FPGA toolchain, based on Project IceStorm, Yosys and Nextpnr. In this way, in the repository you will find the VHDL and Verilog version of simple asynchronous cells and a series of practical examples based on the Lattice iCEstick Evaluation Kit.
NOTE: Currently, only the basic micropipeline demo is available, but this is a very good entry point to implementing asynchronous logic circuits in general and GALS in particular.