• Lucas Russo's avatar
    hdl/modules/*/*/acq_ddr3_read.vhd: change ddr3 addressing · 73f84a4a
    Lucas Russo authored
    Due to recent changes in the wey we perform DDR3 transactions,
    we unified the reading (used for simulation purposes) module
    to perform only full data reads (UI data width) and incrementing
    the address accordingly.
    
    Also, cleanup some code comments.
    73f84a4a
acq_ddr3_read.vhd 16.6 KB