The "ce" signal of the IDELAYE2 primitive was hardcoded to '1'.
Clearly a bug when using the primitive in VAR_LOAD mode for Xilinx
7SERIES FPGAs. The correct value is '0' as the "ld" signal controls
"valid" delay value.

With the "ce" signal alwas on, we would have, on each clock cycle,
an increment in the delay value causing sampling errors.

This fixes #38 github issue.